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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Nilesh Parihar
Bhartiya Institute of Engineering & Technology
Economics, Econometrics & Finance

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Real-Time Algorithms and Architectures for several user Channel Detection in Wireless Base Station Receivers Nitish Meena; Nilesh Parihar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 2: July 2015
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (574.28 KB) | DOI: 10.11591/ijres.v4.i2.pp82-98

Abstract

In this paper presents algorithms and architecture designs that can meet real-time requirements of for several user channel estimation and detection in code-division multiple-access-based wireless base-station receivers. Entangled algorithms proposed to implement several user channel assessment and demodulation make their real-time execution difficult on current digital signal processor-based receivers. A based several user channel assessment scheme requiring matrix conversion is draft again from an demodulation perspective for a reduced intricacy, repetitive scheme with a simple fixed-point very large scale integration  architecture. A reduced-intricacy, bit-streaming several user demodulation algorithm that avoids the need for demodulation is also developed for a simple, pipelined VLSI architecture. Thus, we develop real-time solutions for several user channel assessment and demodulation for third-generation wireless systems by: 1) designing the algorithms from a fixed-point execution perspective, without significant loss in error rate performance; 2) task partitioning; and 3) designing bit-streaming fixed-point VLSI architectures that explore pipelining, correspondence, and bit-level computations to achieve real-time with minimum area overhead.
Co-Authors Nitish Meena