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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
P.Radhika Ramya
Vignan University
Economics, Econometrics & Finance

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Optimization and Implementation of Reversible BCD Adder in Terms of Number of Lines P.Radhika Ramya; Y.Sudha Vani
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 1: March 2013
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (226.826 KB) | DOI: 10.11591/ijres.v2.i1.pp21-26

Abstract

The Reversible logic plays an important role to obtain the minimal energy dissipation. It is the main requirement in the low power digital design. To implement a reversible function some additional lines are required. Sometimes it is more than the primary inputs which leads to increased size of the circuit. Hence the reducing the number of circuit lines is one of the major criterion in reversible logic. The general idea is to merge the garbage output lines with appropriate constant input lines. In this work, Toffoli gate implementation of BCD adder and press gate implementation of BCD adder is taken and an optimization algorithm has been applied to reduce the number of lines in the circuit. The kit used to implement the design is Vertex5 in which both the area and delay are analyzed.
Co-Authors Y.Sudha Vani