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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
M. Anitha
Sathyabama University
Economics, Econometrics & Finance

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A New-High Speed-Low Power-Carry Select Adder Using Modified GDI Technique M. Anitha; J.Princy Joice; Rexlin Sheeba.I
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 3: November 2015
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (69.77 KB) | DOI: 10.11591/ijres.v4.i3.pp173-177

Abstract

Adders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder.The proposed method aims on GDI(Gate Diffusion Input) Technique. Modified GDI is a novel technique for low power digital circuits design further to reduce the swing degradation problem. This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder.This technique can be used to reduce the number of transistors compared to conventional CSLA and made comparison with known conventional adders which gives that the usage of carry-strength signals allows high-speed adders to be realised at lower cost as well as consuming lower power than previous designs. Hence, this paper we are concentrating on the area level &we are reducing the power using modified GDI logic.
Co-Authors J.Princy Joice Rexlin Sheeba.I