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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)

Sanket Suresh Naik Dessai

Department of Computer Engineering, M S Ramaiah School of Advanced Studies in collaboration with Coventry University,

Author-ID : 2407618

Economics, Econometrics & Finance

Published : 4 Documents Claim Missing Document

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Articles

Development of Wireless Sensor Network for Traffic Monitoring Systems Sanket Suresh Naik Dessai
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 3: November 2014
Publisher : Institute of Advanced Engineering and Science

Traffic congestion has been a major problem on roads around the world. In addition, there is increase in volume of traffic vehicle density at a steady rate. Thus traffic on major roads has to be controlled to keep the traffic flowing at an acceptable rate. Several schemes for replacing the predominantly used Round Robin (RR) scheme for reducing congestion at traffic junctions have been proposed. Dynamic traffic control schemes adapt to the changing traffic by monitoring the state (such as the number queued up on each lane.). These need appropriate sensing and monitoring systems. In this paper a traffic monitoring and control system based on AMR (Anistropic Magneto Resistive) vehicle sensors, wireless sensor network and a proiritised Weighted Round Robin (WRR) scheduling technique, is developed.AMR sensors installed in road pavement detect the number of vehicles waiting in a traffic lane. The AMR sensors are connected to the master controller to form a Zigbee based sensor network. The master node consists of an ARM processor integrated with a Zigbee masternode. The traffic control algorithm is implemented at master node which is responsible for taking traffic signaling decision. It receives sensor data from all the lanes. A two level priority algorithm with weighted round robin scheduling, where first and second maximum weighted lane are to pass the signal is developed, To avoid starving the least loaded lanes, a cycle of normal round robin scheduling is performed after four rounds of proiritised weighted round robin schedule. The proposed algorithm is simulated and compared with the standard round robin algorithm. The developed algorithm decreases the average waiting time for a commuter while maintaining the average throughput up to average loads. The development traffic monitoring system is successfully demonstrated for a four lane junction.

Design and Implementation of an Ethernet MAC IP Core for Embedded Applications Sanket Suresh Naik Dessai
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 3: November 2014
Publisher : Institute of Advanced Engineering and Science

An IP (intellectual property) core is a block of logic or data that is used in making a field programmable gate array (FPGA) or application-specific integrated circuit (ASIC) for a product. As essential elements of design reuse, IP cores are part of the growing electronic design automation (EDA) industry trend towards repeated use of previously designed components. Ethernet continues to be one of the most popular LAN technologies. Due to the robustness resulting from its wide acceptance and deployment, there has been an attempt to build Ethernet-based real-time control networks for manufacturing automation. There is a growing demand for low cost, power efficient MAC IP Core for various embedded applications. In this paper a project is discussed to design an Ethernet MAC IP Core solution for such embedded applications. The proposed 10_100_1000 Mbps tri-mode Ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed to use less than 2000 LCs/LEs to implement full function. It will use inferred RAMs and PADs to reduce technology dependence. To increase the flexibility, three optional modules can be added to or removed from the project. A GUI configuration interface, created by Tcl/tk script language, is convenient for configuring optional modules, FIFO depth and verification parameters. Furthermore, a verification system was designed with Tcl/tk user interface, by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum. A solution which would consume a smaller part of the targeted FPGA, and thus giving room for other on-chip peripherals or enable the use of a smaller sized FPGA. To employ a smaller FPGA is desirable since it would reduce power consumption and device price.

Design and Development of Texture Filtering Architecture for GPU Application Using Reconfigurable Computing Sanket Suresh Naik Dessai
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 3: November 2012
Publisher : Institute of Advanced Engineering and Science

Graphical Processing Units (GPUs) have become an integral part of today’s mainstream computing systems. They are also being used as reprogrammable General Purpose GPUs (GP-GPUs) to perform complex scientific computations. Reconfigurability is an attractive approach to embedded systems allowing hardware level modification. Hence, there is a high demand for GPU designs based on reconfigurable hardware. The texture filter unit is designed to process geometric data like vertices and convert these into pixels on the screen. This process involves number of operations, like circle and cube generation, rotator, and scaling. The texture filter unit is designed with all necessary hardware to deal with all the different filtering operations. The designed texture filtering units are modelled in Verilog on Altera Quartus II and simulated using ModelSim tools. The functionality of the modelled blocks is verified using test inputs in the simulator.Circle and cube coordinates are generated for circle and cube generation. The work can form the basis for designing a complete reconfigurable GPU.

Software Design and Development of Beverage Vending Machine System Using ARM Architecture with LPC2148 Sanket Suresh Naik Dessai
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 1: March 2015
Publisher : Institute of Advanced Engineering and Science

Beverage vending machine systems are becoming popular in the Indian market.These systems are today available in Indian MNCs and some top rated restaurants and hotels.In most systems the operation are carried manually by the operator in which the billing and change making is carried out by the owner who runnig the shop or restaurant.In India tea and coffee habits were cultured by the colonial rule of the British and the Portuguese,even tody the colonial rule had been over but the habits of tea and coffee beverage consumptions becomes as the routine daily life.Hence there is a need to understand beverage vending machine systems to serve the Indian Market. In this paper,a critical analysis of requirement has been carried out and the system design had been arrived at.The system requirement demand an ARM based controller for better system performance.To meet the system performance criteria and richest of peripherals an LPC2148 with low cost had been selected.The system is more efficient to analyse the change making and the identification had been carried out using the motors,LCDs,water heater,solenoid valve,money box,change making and dispensing unit. The system is tested and validated for the specified test cases.The milk motor run for 10 rotations to drive 200 milligrams of milk powder to the container to make to tea or coffee beverage.In this system a stepper motor had been used can be replaced by using dc motors to avaoid power losses.In future an ATM or credit card based payment system can be incorporated to these systems.

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