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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Matias Javier Oliva
Universidad Nacional de La Plata (UNLP) Instituto de investigaciones en electronica control y procesamiento de datos (LEICI) Grupo de instrumentacion biomedica industrial y cientifica (GIBIC)
Economics, Econometrics & Finance

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SoC-FPGA systems for the acquisition and processing of electroencephalographic signals Matias Javier Oliva; Pablo Andrés García; Enrique Mario Spinelli; Alejandro Luis Veiga
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 3: November 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v10.i3.pp237-248

Abstract

Real-time acquisition and processing of electroencephalographic signals have promising applications in the implementation of brain-computer interfaces. These devices allow the user to control a device without performing motor actions, and are usually made up of a biopotential acquisition stage and a personal computer (PC). This structure is very flexible and appropriate for research, but for final users it is necessary to migrate to an embedded system, eliminating the PC from the scheme. The strict real-time processing requirements of such systems justify the choice of a system on a chip field-programmable gate arrays (SoC-FPGA) for its implementation. This article proposes a platform for the acquisition and processing of electroencephalographic signals using this type of device, which combines the parallelism and speed capabilities of an FPGA with the simplicity of a general-purpose processor on a single chip. In this scheme, the FPGA is in charge of the real-time operation, acquiring and processing the signals, while the processor solves the high-level tasks, with the interconnection between processing elements solved by buses integrated into the chip. The proposed scheme was used to implement a brain-computer interface based on steady-state visual evoked potentials, which was used to command a speller. The first tests of the system show that a selection time of 5 seconds per command can be achieved. The time delay between the user’s selection and the system response has been estimated at 343 µs.
Co-Authors Alejandro Luis Veiga Enrique Mario Spinelli Pablo Andrés García