Article Per Year (5 Year)
p-Index From 2021 - 2026
0
P-Index
This Author published in this journals
All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Shruthi AV
Visveswaraya Technological University
Economics, Econometrics & Finance

Published : 1 Documents Claim Missing Document
Claim Missing Document
Check
Articles

Found 1 Documents
Search

 1 
Low Power VLSI Design and Implementation of Area-Optimized 256-bit AEStandard for Real Time Images on Vertex 5 Shruthi AV; Electa Alice; Mohammed Bilal
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 2: July 2013
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (252.908 KB) | DOI: 10.11591/ijres.v2.i2.pp83-88

Abstract

A new Vertex6-chipscope based implementation scheme of the AES-256 (Advanced Encryption Standard, with 256-bit key) encryption and decryption algorithm is proposed in this paper. For maintaining the speed of encryption and decryption, the pipelining technology is applied and the mode of data transmission is modified in this design so that the chip size can be reduced. The 256-bit plaintext and the 256- bit initial key, as well as the 256-bit output of cipher-text, are all divided into four 32-bit consecutive units respectively controlled by the clock. In this novel work, substantial improvement in performance in terms of area, power and dynamic speed has been obtained.
Co-Authors Electa Alice Mohammed Bilal