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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Sanket Dessai
Ramaiah University of Applied Sciences
Economics, Econometrics & Finance

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Design and Development of IP for Modified Haar Wavelet Transform (MHWT) Image Fusion using FPGA Sumant S Yaliagr; Sanket Dessai
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 1: March 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (704.45 KB) | DOI: 10.11591/ijres.v7.i1.pp57-66

Abstract

The fast growth in the field of digital imaging applications in remote sensing, bio medical and other satellite applications had created an architecture studies for image fusion in capable to store large amount of data and process. An algorithm considered for the process of image fusion for implementation of FPGA is Modified Haar Wavelet Transform (MHWT) based image fusion where at the time four pixels are consider in calculation of different bands as compared to conventional Haar wavelet based image fusion. The process of modification uses far less memory and computation power. The FPGA implementation of MHWT based image fusion is done on Digilent development board with Spartan 6 series FPGA. The architecture is developed in VHDL. The timing analysis is done and report is obtained for I/O interactions, memory units etc. The architecture is made to run in cosimulation with Simulink. The design is tested with different kinds of images and run successfully. The visual analysis of the resultant fused image is achived and observed.
Processor performance metrics analysis and implementation for MIPS using an open source OS Varuna Eswer; Sanket Dessai
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 2: July 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v10.i2.pp137-148

Abstract

Processor efficiency is a important in embedded system. The efficiency of the processor depends on the L1 cache and translation lookaside buffer (TLB). It is required to understand the L1 cache and TLB performances during varied load for the execution on the processor and hence studies the performance of the varying load and its performance with caches with MIPS and operating system (OS) are studied in this paper. The proposed methods of implementation in the paper considers the counting of the instruction execution for respective cache and TLB management and the events are measured using a dedicated counters in software. The software counters are used as there are limitation to hardware counters in the MIPS32. Twentyseven metrics are considered for analysis and proper identification and implemented for the performance measurement of L1 cache and TLB on the MIPS32 processor. The generated data helps in future research in compiler tuning, memory management design for OS, analyzing architectural issues, system benchmarking, scalability, address space analysis, studies of bus communication among processor and its workload sharing characterization and kernel profiling.
Co-Authors Sumant S Yaliagr Varuna Eswer