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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Sowmya K B
RVCE,Bengaluru
Economics, Econometrics & Finance

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A system verilog approach for verification of memory controller Sowmya K B; Gagana P
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (387.86 KB) | DOI: 10.11591/ijres.v9.i2.pp153-157

Abstract

Memory performance has become the major bottleneck to improve the overall performance of the computer system. By using memory controller, there is effective control of data between processor and memory. In this paper, a memory controller for interfacing Synchronous Static Random Access Memory (SSRAM), Synchronous Dynamic Random Access Memory (SDRAM), Read Only Memory (ROM) and FLASH which is Electrically Erasable Programmable Read-Only Memory is designed and a coverage driven Constraint random verification environment is built for the designed memory controller. Verification plays an important role in any design flow as it is done before silicon development. It is done at time of product development for quality checking and bug fixing in design.
Co-Authors Gagana P