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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
R. Brindha
Avinashilingam institute for home science and higher education for woman
Economics, Econometrics & Finance

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512 bit-SHA3 design approach and implementation on field programmable gate arrays S. Neelima; R. Brindha
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 3: November 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (616.163 KB) | DOI: 10.11591/ijres.v8.i3.pp169-174

Abstract

In this work, the authors consider the newly selected Hash Secure (SHA-3) algorithm on FPGA Gateway. The design is logically optimized for zone efficiency by combining the Rho steps and the one-pass algorithm. Logically recording these three steps registers leads to usage 16% of the logical resources for all implementations. This in turn reduces the latency and increases the maximum operating frequency of the project. It uses only 240 sections and has a frequency of 301.02 MHz compared to the design results with the previous FPGA implementation described in SHA3-512, the design shows the Throughput-Per-Slice (TPS) ratio of 30, 1.
Co-Authors S. Neelima