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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Chakrapani Kannan
Sastra Univeristy
Economics, Econometrics & Finance

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NIOS II Based Secure Test Wrapper Design for Testing Cryptographic Algorithms Chakrapani Kannan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 3: November 2015
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (737.366 KB) | DOI: 10.11591/ijres.v4.i3.pp185-191

Abstract

Cryptographic algorithms need infrastructure for testing them against security attacks. Normally many methods are proposed for testing these cryptographic primitives. Normal designs cannot be applied to all types of cryptographic chips. Usually build in self test is applied for the intellectual property chips for testing them. But it suffers from many problems such as side channel attack, backholes, high area overhead, etc.., to overcome all these drawbacks test wrapper is designed and tested using NIOS II economy soft core processor.  NIOS II is utilized as the soft core processor and cryptographic algorithms are executed. RTL view of these cryptographic circuits is described. Synthesis result shows the chip planner view of the circuits and the area required for the logic elements. NIOS II soft-core processors perform well for testing the cryptographic algorithms. Results with respects to area optimization, memory and speed are discussed. The logic components required for design using NIOS II is optimized. Memory required is also less compare to other processors. Area required is optimized using NIOS II processor and it is flexible for design of complex circuits.
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