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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Varatharajan Ramachandran
Annad University
Economics, Econometrics & Finance

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An Efficient VLSI Architecture for Nonbinary LDPC Decoder with Adaptive Message Control Varatharajan Ramachandran
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 1: March 2015
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (187.539 KB) | DOI: 10.11591/ijres.v4.i1.pp6-12

Abstract

A new decoder architecture for nonbinary low-density parity check (LDPC) codes is presented in this paper to reduce the hardware operational complexity and power consumption. Adaptive message control (AMC) is to achieve the low decoding complexity,  that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. A new horizontal nonbinary LDPC decoder architecture is developed to implement AMC. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefit of the proposed AMC. Simulation results demonstrate that the proposed nonbinary LDPC decoder architecture can significantly reduce hardware operations and power consumption as compared with existing work with negligible performance degradation.
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