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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Sasikumar Sasikumar
SASTRA University
Economics, Econometrics & Finance

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An Optimal Design of CMOS Two Stage Comparator Circuit using Swarm Intelligence Technique Sasikumar Sasikumar; Muthaiah Muthaiah
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 3: November 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (268.487 KB) | DOI: 10.11591/ijres.v7.i3.pp131-137

Abstract

A swarm intelligent based optimization technique named as Flower pollination algorithm (FPA) is applied for the design of the CMOS two stage comparator circuit. The basic idea of FPA mimics the flower pollination process of flowering plants. The input control parameters of FPA improve the exploration and exploitation capabilities of optimization problem. This paper presents the design of a CMOS two-stage comparator circuit using simulation based model called swarm intelligence technique. Simulation results shows that the proposed method is capable to determine the transistor sizes and bias current values of the CMOS comparator. The results obtained from the FPA improved the design performance of comparator in terms of power consumption, MOS transistor area and gain. To investigate the efficiency of proposed approach, comparisons have been carried out with differential evolution (DE) and harmony search (HS) algorithm based circuit design. The performances of FPA based comparator design are better than the previously reported works
Co-Authors Muthaiah Muthaiah