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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Naoufal Raissouni
National School for Applied Sciences of Tetuan, University Abdelmalek Essaadi, Innovation & Telecoms Engineering Research Group. Remote Sensing & Mobile GIS Unit, Mhannech II, B.P 2121 Tetuan, Morocco
Economics, Econometrics & Finance

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AES Encryption Algorithm Hardware Implementation: Throughput and Area Comparison of 128, 192 and 256-bits Key Samir El Adib; Naoufal Raissouni
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 2: July 2012
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (237.701 KB) | DOI: 10.11591/ijres.v1.i2.pp67-74

Abstract

Advanced Encryption Standard (AES) adopted by the National Institute of Standards and Technology (NIST) to replace existing Data Encryption Standard (DES), as the most widely used encryption algorithm in many security applications. Up to today, AES standard has key size variants of 128, 192, and 256-bit, where longer bit keys provide more secure ciphered text output. In the hardware perspective, bigger key size also means bigger area and small throughput. Some companies that employ ultra-high security in their systems may look for a key size bigger than 128-bit AES. In this paper, 128, 192 and 256-bit AES hardware are implemented and compared in terms of throughput and area. The target hardware used in this paper is Virtex XC5VLX50 FPGA from Xilinx. Total area and Throughput results are presented and graphically compared.
Co-Authors Samir El Adib