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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
S.Tamil Selvan
Bharath Institute of Higher Education & Research Chennai
Economics, Econometrics & Finance

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Comparison analysis of three value logic 8T CNTFET SRAM Cell with 6 CMOS SRAM CELL at 32nm technology S.Tamil Selvan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 2: July 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (338.452 KB) | DOI: 10.11591/ijres.v8.i2.pp107-113

Abstract

This paper proposed a new concept of highly SNM and low power SRAM cell using carbon nanotube FETs (CNTFETs) at 18nm technology node. As device physical gate length is reduced to below 65 nm, device non-idealities such as large parameter variations and exponential increase in Dynamic leakage current make the I-V characteristics substantially different from traditional MOSFETs and become a serious obstacle to scale devices. CNFETs have received widespread attention as one of the promising successor to MOSFETs. The proposed circuit was simulated in HSPICE using 32nm Stanford CNFET model. Analysis of the results shows that the proposed CNTFET based 3VL 8T SRAM cell, power dissipation, and stability substantially improved compared with the conventional CMOS 6T SRAM cell by 51% and 58% respectively at the expense of 4% write delay increase.
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