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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Raju Hajare
BMS Institute of Technology and Management
Economics, Econometrics & Finance

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Space-time trellis codes: Field programmable gate array approach Mallikarjuna Gowda C. P.; Raju Hajare
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 3: November 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v9.i3.pp213-223

Abstract

This paper presents an implementation of Space-time Trellis Codes for 4-state on FPGA. To reach the very high data rates provided in STTC, a lot of expensive high-speed Digital Signal Processors (DSPs) should be employed for the real time applications, while it might not be affordable. This fact has motivated in designing dedicated hardware implementations using Field Programmable Gate Array (FPGA) with low cost and power consumption. The hardware device XC3S400, family Xilinx Spartan-3, and package PQ208 are used in this project, in which the STTC encoder and decoder utilizes maximum 10% and 22% as that of available device capacity respectively. The design has been simulated and synthesized successfully in Xilinx integrated software environment.
Co-Authors Mallikarjuna Gowda C. P.