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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Harinath Mandalapu
K L University
Economics, Econometrics & Finance

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FPGA implementation of DS-CDMA Transmitter and Receiver Harinath Mandalapu; B Murali Krishna
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 3: November 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (272.845 KB) | DOI: 10.11591/ijres.v6.i3.pp179-185

Abstract

Direct sequence spread Spectrum (DSSS) is also known as direct sequence code division multiplexing. In direct sequence spread spectrum the stream of information to be transmitted is divided into small pieces each of which is allocated across to a frequency channel across the spectrum. Data signal at the point of transmission is collaborated with a higher data-rate bit sequence (also called chipping code) that divides the data according to a spreading ratio. A redundant chipping code helps the signal resist interference and also enables the original data to be recovered if data bits are damaged during the transmitting. In this project direct sequence spread spectrum principle based code division multiple access (CDMA) transmitter and receiver is implemented on SPARTAN 3E FPGA. The Xilinx synthesis technology (XST) of Xilinx ISE tool used for synthesis of transmitter and receiver on FPGA Spartan 3E.
Co-Authors B Murali Krishna