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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
G. Subramanya Nayak
Manipal University
Economics, Econometrics & Finance

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Implementation of High Speed Vedic Multiplier Using Vertical and Crosswise Algorithm G. Vadiraj; K. Shivanand; B. Sampat; G. Subramanya Nayak
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 1: March 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (389.585 KB) | DOI: 10.11591/ijres.v6.i1.pp36-40

Abstract

Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate (MAC) and inner product are some of the frequently used operations in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors in its arithmetic and logic unit. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. In this project, the comparative study of Vedic multiplier and Sequential multiplier is done for low power requirement and high speed. The proposed architecture is based on the Vertical and Crosswise algorithm of ancient Indian Vedic Mathematics, which increases the speed of multiplier by reducing the number of clock cycles thus achieving the greater speed of the processor or system.
Co-Authors B. Sampat G. Vadiraj K. Shivanand