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All Journal TELKOMNIKA (Telecommunication Computing Electronics and Control)
Neelima Koppala
Research Scholar, Department of ECE, JNTUA, Ananthapuramu,
Computer Science & IT

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Low overhead optimal parity codes Neelima Koppala; Chennapalli Subhas
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 20, No 3: June 2022
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v20i3.23301

Abstract

The error detecting and correcting codes are used in critical applications like in intensive care units, defense applications, and require highly reliable data. This brief focuses on codes to detect and correct adjacent errors within a single clock cycle by using modulo-2 addition of data bits for parity generation, syndrome calculation, error location identification and correction by improving code rate and minimizing bit overhead. The optimal parity codes devised can correct odd number of adjacent errors upto (N/2)-1 data bits when compared with the existing codes with less delay. Four optimal codes are proposed using existing decimal matrix codes properties. The proposed codes prove better in terms of area, delay, power, bit overhead, code rate, code efficiency, and with good reliability. The components are developed in veriloghardware description language and verified for zynq 7000 series field programmable gate array in xilinx integrated synthesis environment 14.5 Tool. Among the codes devised, optimal code-4 proves to be a better code with 65.3% code rate and 53.12% bit overhead. Also when compared with other codes, it uses 33.3% less area and 1.89% less power delay product for encoder and 32.2% less area and 0.36% power delay product for decoder respectively.
Co-Authors Chennapalli Subhas