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Zhongxun Wang
Yantai University
Computer Science & IT

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Binary LDPC Codes Decoding Algorithm Based on MRF and FPGA Implementation Zhongxun Wang; Wenqiang Wu
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 14, No 4: December 2016
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v14i4.4158

Abstract

The improved LDPC code decoding algorithm mainly refereed to improving decoding performance or reducing the decoding computation complexity. No matter hard decision or soft decision LDPC code decoding algorithm, we can get all ring number by one test, instead of testing each long ring number, after optimizing ring detection algorithm. We putted forward the application of Gaussian Markov Random Field model to realize the source parameter estimation, and make logarithmic likelihood ratio correction of bit sequence received by the channel decoding end. Joining source residual redundancy information to increase the decoder error correction ability. Source estimation adaptive variable can correct coefficient, and it was regulated by error rate. Under the condition that computational complexity increasedlittlely, the LDPC code decoding algorithm based on MRF effectively improved the decoding performance and implemented the improvement of LDPC code decoding algorithm .In the end, we realized the decoding algorithm by using FPGA.
Non-binary LDPC Decoder Design over Rayleigh Channel for FPGA Implementation Zhongxun Wang; Juan Hui
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 14, No 4: December 2016
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v14i4.4157

Abstract

This paper is under in-depth investigation due to suspicion of possible plagiarism on a high similarity indexLow Density Parity Check Code（LDPC） is a kind of linear block codes based on sparse check matrix. As a kind of channel coding, whose error performance approach Shannon limits, it has better error correction capability, more flexible structure and lower decoding complexity. Currently most of the LDPC code researches are on the premise of the AWGN channel and BSC channel, which mainly in the range of the binary LDPC codes. According to the above problem, this paper analyzes the various decoding performance of non-binary LDPC codes in Rayleigh channel, and realizes a non-binary LDPC decoder in Rayleigh channel through the FPGA design. The paper begins with an overall discussion of issues surrounding the use of non-binary LDPC codes. And then the bit-error-rate (BER) performances of different non-binary LDPC codes decoding algorithm are compared on the independent Rayleigh fading channel. Finally, this decoder design is implemented based on 5CSEMA5F31C6 FPGA (devised by Altera Company) to illustrate the concepts discussed in the paper.
Co-Authors Juan Hui Wenqiang Wu