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All Journal TELKOMNIKA (Telecommunication Computing Electronics and Control) Indonesian Journal of Electrical Engineering and Computer Science
Nasir Shaikh Husin
Universiti Teknologi Malaysia
Computer Science & IT

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Stochastic Computing Correlation Utilization in Convolutional Neural Network Basic Functions Hamdan Abdellatef; Mohamed Khalil Hani; Nasir Shaikh Husin; Sayed Omid Ayat
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 16, No 6: December 2018
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v16i6.8955

Abstract

In recent years, many applications have been implemented in embedded systems and mobile Internet of Things (IoT) devices that typically have constrained resources, smaller power budget, and exhibit "smartness" or intelligence. To implement computation-intensive and resource-hungry Convolutional Neural Network (CNN) in this class of devices, many research groups have developed specialized parallel accelerators using Graphical Processing Units (GPU), Field-Programmable Gate Arrays (FPGA), or Application-Specific Integrated Circuits (ASIC). An alternative computing paradigm called Stochastic Computing (SC) can implement CNN with low hardware footprint and power consumption. To enable building more efficient SC CNN, this work incorporates the CNN basic functions in SC that exploit correlation, share Random Number Generators (RNG), and is more robust to rounding error. Experimental results show our proposed solution provides significant savings in hardware footprint and increased accuracy for the SC CNN basic functions circuits compared to previous work.
An Empirical Evaluation of Topologies for Large Scale NoC Mehdi Baboli; Nasir Shaikh Husin
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 12: December 2014
Publisher : Institute of Advanced Engineering and Science

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Abstract

In the past decades, processing power has achieved considerable gains. Researchers proposed faster uniprocessors that are capable of improving the instruction level parallelism through out-of-order implementation for increasing the performance quality of the existing network-on-chip (NoC). Although, the reducing returns of the performance of uniprocessor architecture caused multiprocessors to be integrated on a chip. In this paper, we selected a famous popular NoC topology, i.e., mesh, and evaluated it in terms of different figures of merit e.g., latency, power consumption, and power/throughput ratio under different routing algorithms, number of buffer, and hotspot traffic models. We selected two size of NoC, 12×12 and 16×16, as large scale NoC. We investigated all characteristics and measured latency, maximum delay, and total energy by Noxim simulator. In this paper, we demonstrated that when the network size and number of buffer were large, no routing algorithm could contribute to improve network performance. This is because the routing algorithms had the same performance in the large scale NoCs and they could not solve problems alone. Therefore, for a large scale system, the topology has a major impact on the performance and cost of the network. http://dx.doi.org/10.11591/telkomnika.v12i12.6840 
Co-Authors Hamdan Abdellatef Mehdi Baboli Mohamed Khalil Hani Sayed Omid Ayat