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128 mA CMOS LDO with 108 db PSRR at 2.4 MHz frequency Astrie Nurasyeila Fifie; Yan Chiew Wong
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 17, No 5: October 2019
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v17i5.12795

A low dropout (LDO) voltage regulator with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented in this paper. Large 1µF off-chip load capacitor is used to achieve the high PSRR. However, this decreases the gain and pushes the LDO’s output pole to lower frequency causing the circuit to become unstable. The proposed LDO uses rail-to-rail folded cascode amplifier to compensate the gain and stability problems. 2nd order curvature characteristic is used in bandgap voltage reference circuit that is applied at the input of the amplifier to minimize the TC. The characteristic is achieved by implementing MOSFET transistors operate in weak and strong inversions. The LDO is designed using 0.18µm CMOS technology and achieves a constant 1.8V output voltage for input voltages from 3.2V to 5V and load current up to a 128mA at temperature between -40°C to 125°C. The proposed LDO is targeted for RF application which has stringent requirement on noise rejection over a broad range of frequency.

A 30mV input battery-less power management system Jim Hui Yap; Yan Chiew Wong
Bulletin of Electrical Engineering and Informatics Vol 8, No 4: December 2019
Publisher : Institute of Advanced Engineering and Science

This paper presents a fully-integrated on chip battery-less power management system through energy harvesting circuit developed in a 130nm CMOS process. A 30mV input voltage from a TEG is able to be boosted by the proposed Complementary Metal-Oxide-Semiconductor (CMOS) voltage booster and a dynamic closed loop power management to a regulated 1.2V. Waste body heat is harvested through Thermoelectric energy harvesting to power up low power devices such as Wireless Body Area Network. A significant finding where 1 Degree Celsius thermal difference produces a minimum 30mV is able to be boosted to 1.2V. Discontinuous Conduction Mode (DCM) digital control oscillator is the key component for the gate control of the proposed voltage booster. Radio Frequency (RF) rectifier is utilized to act as a start-up mechanism for voltage booster and power up the low voltage closed loop power management circuit. The digitally control oscillator and comparator are able to operate at low voltage 600mV which are powered up by a RF rectifier, and thus to kick-start the voltage booster.

Design consideration in low dropout voltage regulator for batteryless power management unit Mohamad Khairul bin Mohd Kamel; Yan Chiew Wong
Bulletin of Electrical Engineering and Informatics Vol 8, No 4: December 2019
Publisher : Institute of Advanced Engineering and Science

Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology.

A 30mV input battery-less power management system Jim Hui Yap; Yan Chiew Wong
Bulletin of Electrical Engineering and Informatics Vol 8, No 4: December 2019
Publisher : Institute of Advanced Engineering and Science

This paper presents a fully-integrated on chip battery-less power management system through energy harvesting circuit developed in a 130nm CMOS process. A 30mV input voltage from a TEG is able to be boosted by the proposed Complementary Metal-Oxide-Semiconductor (CMOS) voltage booster and a dynamic closed loop power management to a regulated 1.2V. Waste body heat is harvested through Thermoelectric energy harvesting to power up low power devices such as Wireless Body Area Network. A significant finding where 1 Degree Celsius thermal difference produces a minimum 30mV is able to be boosted to 1.2V. Discontinuous Conduction Mode (DCM) digital control oscillator is the key component for the gate control of the proposed voltage booster. Radio Frequency (RF) rectifier is utilized to act as a start-up mechanism for voltage booster and power up the low voltage closed loop power management circuit. The digitally control oscillator and comparator are able to operate at low voltage 600mV which are powered up by a RF rectifier, and thus to kick-start the voltage booster.

Design consideration in low dropout voltage regulator for batteryless power management unit Mohamad Khairul bin Mohd Kamel; Yan Chiew Wong
Bulletin of Electrical Engineering and Informatics Vol 8, No 4: December 2019
Publisher : Institute of Advanced Engineering and Science

Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology.

A 30mV input battery-less power management system Jim Hui Yap; Yan Chiew Wong
Bulletin of Electrical Engineering and Informatics Vol 8, No 4: December 2019
Publisher : Institute of Advanced Engineering and Science

This paper presents a fully-integrated on chip battery-less power management system through energy harvesting circuit developed in a 130nm CMOS process. A 30mV input voltage from a TEG is able to be boosted by the proposed Complementary Metal-Oxide-Semiconductor (CMOS) voltage booster and a dynamic closed loop power management to a regulated 1.2V. Waste body heat is harvested through Thermoelectric energy harvesting to power up low power devices such as Wireless Body Area Network. A significant finding where 1 Degree Celsius thermal difference produces a minimum 30mV is able to be boosted to 1.2V. Discontinuous Conduction Mode (DCM) digital control oscillator is the key component for the gate control of the proposed voltage booster. Radio Frequency (RF) rectifier is utilized to act as a start-up mechanism for voltage booster and power up the low voltage closed loop power management circuit. The digitally control oscillator and comparator are able to operate at low voltage 600mV which are powered up by a RF rectifier, and thus to kick-start the voltage booster.

Design consideration in low dropout voltage regulator for batteryless power management unit Mohamad Khairul bin Mohd Kamel; Yan Chiew Wong
Bulletin of Electrical Engineering and Informatics Vol 8, No 4: December 2019
Publisher : Institute of Advanced Engineering and Science

Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology.

Current mismatch reduction in charge pumps using regulated current stealing-injecting transistors for PLLs Mohd Khairi Zulkalnain; Yan Chiew Wong
Indonesian Journal of Electrical Engineering and Computer Science Vol 24, No 1: October 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v24.i1.pp61-69

A charge pump for phase locked loops (PLL) with a novel current mismatch compensation technique is proposed. The proposed circuit uses a simple yet effective current stealing-injecting (CSI) technique and feedback to reduce mismatch between the negative-channel-metal-oxide (NMOS) and positive-channel-metal-oxide (PMOS) transistors. The current stealing transistor steals the current from a replica branch and mirrors it to the output where it is added to the output branch by the injecting transistor. A feedback mechanism is used to set the drain voltages of both branches to be equal and mitigate channel length modulation and ensure high accuracy. The proposed circuit was designed on Silterra 130nm technology and simulated using Cadence Spectre. The simulation results show that the proposed circuit yields a maximum of 0.107% and minimum of 0.00465% current mismatch while operating at a low supply voltage of 800mV for a range of 100mV to 700mV. The proposed design uses only one rail-to-rail op amp for compensating the mismatch and an addition of 4 transistors and utilizing 75% of the supply voltage for high voltage controlled oscillator (VCO) tuning range.

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