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All Journal Bulletin of Electrical Engineering and Informatics Bulletin of Electrical Engineering and Informatics Bulletin of Electrical Engineering and Informatics Indonesian Journal of Electrical Engineering and Computer Science
T. N. T. Yaakub
Universiti Teknologi Mara
Computer Science & IT Electrical & Electronics Engineering Engineering

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Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor S. L. M. Hassan; N. Sulaiman; S. S. Shariffudin; T. N. T. Yaakub
Bulletin of Electrical Engineering and Informatics Vol 7, No 2: June 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (648.597 KB) | DOI: 10.11591/eei.v7i2.1167

Abstract

Fast Fourier transform (FFT) processor is a prevailing tool in converting signal in time domain to frequency domain. This paper provides signal-to-noise ratio (SNR) study on 16-point pipelined FFT processor implemented on field-programable gate array (FPGA). This processor can be used in vast digital signal applications such as wireless sensor network, digital video broadcasting and many more. These applications require accuracy in their data communication part, that is why SNR is an important analysis. SNR is a measure of signal strength relative to noise. The measurement is usually in decibles (dB). Previously, SNR studies have been carried out in software simulation, for example in Matlab. However, in this paper, pipelined FFT and SNR modules are developed in hardware form. SNR module is designed in Modelsim using Verilog code before implemented on FPGA board. The SNR module is connected directly to the output of the pipelined FFT module. Three different pipelined FFT with different architectures were studied. The result shows that SNR for radix-8 and R4SDC FFT architecture design are above 40dB, which represent a very excellent signal. SNR module on the FPGA and the SNR results of different pipelined FFT architecture can be consider as the novelty of this paper.
Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor S. L. M. Hassan; N. Sulaiman; S. S. Shariffudin; T. N. T. Yaakub
Bulletin of Electrical Engineering and Informatics Vol 7, No 2: June 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (648.597 KB) | DOI: 10.11591/eei.v7i2.1167

Abstract

Fast Fourier transform (FFT) processor is a prevailing tool in converting signal in time domain to frequency domain. This paper provides signal-to-noise ratio (SNR) study on 16-point pipelined FFT processor implemented on field-programable gate array (FPGA). This processor can be used in vast digital signal applications such as wireless sensor network, digital video broadcasting and many more. These applications require accuracy in their data communication part, that is why SNR is an important analysis. SNR is a measure of signal strength relative to noise. The measurement is usually in decibles (dB). Previously, SNR studies have been carried out in software simulation, for example in Matlab. However, in this paper, pipelined FFT and SNR modules are developed in hardware form. SNR module is designed in Modelsim using Verilog code before implemented on FPGA board. The SNR module is connected directly to the output of the pipelined FFT module. Three different pipelined FFT with different architectures were studied. The result shows that SNR for radix-8 and R4SDC FFT architecture design are above 40dB, which represent a very excellent signal. SNR module on the FPGA and the SNR results of different pipelined FFT architecture can be consider as the novelty of this paper.
Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor S. L. M. Hassan; N. Sulaiman; S. S. Shariffudin; T. N. T. Yaakub
Bulletin of Electrical Engineering and Informatics Vol 7, No 2: June 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (648.597 KB) | DOI: 10.11591/eei.v7i2.1167

Abstract

Fast Fourier transform (FFT) processor is a prevailing tool in converting signal in time domain to frequency domain. This paper provides signal-to-noise ratio (SNR) study on 16-point pipelined FFT processor implemented on field-programable gate array (FPGA). This processor can be used in vast digital signal applications such as wireless sensor network, digital video broadcasting and many more. These applications require accuracy in their data communication part, that is why SNR is an important analysis. SNR is a measure of signal strength relative to noise. The measurement is usually in decibles (dB). Previously, SNR studies have been carried out in software simulation, for example in Matlab. However, in this paper, pipelined FFT and SNR modules are developed in hardware form. SNR module is designed in Modelsim using Verilog code before implemented on FPGA board. The SNR module is connected directly to the output of the pipelined FFT module. Three different pipelined FFT with different architectures were studied. The result shows that SNR for radix-8 and R4SDC FFT architecture design are above 40dB, which represent a very excellent signal. SNR module on the FPGA and the SNR results of different pipelined FFT architecture can be consider as the novelty of this paper.
Characterizations of electrode geometrical shape for dielectrophoresis N. Burham; A. A. M. Shahar; A. A. Aziz; T. N. T. Yaakub; N. Khairuddin
Indonesian Journal of Electrical Engineering and Computer Science Vol 15, No 2: August 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v15.i2.pp671-677

Abstract

This paper presents a characterization of geometrical shape on dielectrophoresis by determining and analysing the geometrical shape of electrodes. The structure or geometrical shape of dielectrophoresis electrode is design using COMSOL software to determine the maximum trapping efficiency of particles. The trapping efficiency of particles can be evaluated by analysing the best electrical gradient and investigated the behaviour of the particles if the existence of a non-uniform electric field.  There are three geometrical shapes have been designed which is, peel chain shape, castle wall shape and comb shape. Each of the geometrical shapes have different magnetic field produce, hence each of the design have specific application. Furthermore, these three designed are analysed by varying the material of the electrode for the best trapping efficiency. From the various and previous study, for maximum trapping efficiency the shape used is peel chain shape which is suitable for biological and non-biological particles separation. But for the castle wall and comb shape is the most suitable for biological particles such as red blood cell and bacteria trapping. As for the result obtain, it is proven that peel chain shape could achieve maximum electrical gradient to trap biological or non-biological particles in the future.
Co-Authors A. A. Aziz A. A. M. Shahar N. Burham N. Khairuddin N. Sulaiman S. L. M. Hassan S. S. Shariffudin