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A low quiescent current low dropout voltage regulator with self-compensation Chu-Liang Lee; Roslina Mohd Sidek; Nasri Sulaiman; Fakhrul Zaman Rokhani
Bulletin of Electrical Engineering and Informatics Vol 8, No 1: March 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (878.013 KB) | DOI: 10.11591/eei.v8i1.1385

Abstract

This paper proposed a low quiescent current low-dropout voltage regulator (LDO) with self-compensation loop stability. This LDO is designed for Silicon-on-Chip (SoC) application without off-chip compensation capacitor. Worst case loop stability phenomenon happen when LDO output load current (Iload) is zero. The second pole frequency decreased tremendously towards unity-gain frequency (UGF) and compromise loop stability. To prevent this, additional current is needed to keep the output in low impedance in order to maintain second pole frequency. As Iload slowly increases, the unneeded additional current can be further reduced. This paper presents a circuit which performed self-reduction on this current by sensing the Iload. On top of that, a self-compensation circuit technique is proposed where loop stability is selfattained when Iload reduced below 100μA. In this technique, unity-gain frequency (UGF) will be decreaed and move away from second pole in order to attain loop stability. The decreased of UGF is done by reducing the total gain while maintaining the dominant pole frequency. This technique has also further reduced the total quiescent current and improved the LDO’s efficiency. The proposed LDO exhibits low quiescent current 9.4μA and 17.7μA, at Iload zero and full load 100mA respectively. The supply voltage for this LDO is 1.2V with 200mV drop-out voltage. The design is validated using 0.13μm CMOS process technology.
A low quiescent current low dropout voltage regulator with self-compensation Chu-Liang Lee; Roslina Mohd Sidek; Nasri Sulaiman; Fakhrul Zaman Rokhani
Bulletin of Electrical Engineering and Informatics Vol 8, No 1: March 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (1677.161 KB) | DOI: 10.11591/eei.v8i2.1385

Abstract

This paper proposed a low quiescent current low-dropout voltage regulator (LDO) with self-compensation loop stability. This LDO is designed for Silicon-on-Chip (SoC) application without off-chip compensation capacitor. Worst case loop stability phenomenon happen when LDO output load current (Iload) is zero. The second pole frequency decreased tremendously towards unity-gain frequency (UGF) and compromise loop stability. To prevent this, additional current is needed to keep the output in low impedance in order to maintain second pole frequency. As Iload slowly increases, the unneeded additional current can be further reduced. This paper presents a circuit which performed self-reduction on this current by sensing the Iload. On top of that, a self-compensation circuit technique is proposed where loop stability is self-attained when Iload reduced below 100μA. In this technique, unity-gain frequency (UGF) will be decreaed and move away from second pole in order to attain loop stability. The decreased of UGF is done by reducing the total gain while maintaining the dominant pole frequency. This technique has also further reduced the total quiescent current and improved the LDO’s efficiency. The proposed LDO exhibits low quiescent current 9.4μA and 17.7μA, at Iload zero and full load 100mA respectively. The supply voltage for this LDO is 1.2V with 200mV drop-out voltage. The design is validated using 0.13μm CMOS process technology.
A low quiescent current low dropout voltage regulator with self-compensation Chu-Liang Lee; Roslina Mohd Sidek; Nasri Sulaiman; Fakhrul Zaman Rokhani
Bulletin of Electrical Engineering and Informatics Vol 8, No 1: March 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (1677.161 KB) | DOI: 10.11591/eei.v8i2.1385

Abstract

This paper proposed a low quiescent current low-dropout voltage regulator (LDO) with self-compensation loop stability. This LDO is designed for Silicon-on-Chip (SoC) application without off-chip compensation capacitor. Worst case loop stability phenomenon happen when LDO output load current (Iload) is zero. The second pole frequency decreased tremendously towards unity-gain frequency (UGF) and compromise loop stability. To prevent this, additional current is needed to keep the output in low impedance in order to maintain second pole frequency. As Iload slowly increases, the unneeded additional current can be further reduced. This paper presents a circuit which performed self-reduction on this current by sensing the Iload. On top of that, a self-compensation circuit technique is proposed where loop stability is self-attained when Iload reduced below 100μA. In this technique, unity-gain frequency (UGF) will be decreaed and move away from second pole in order to attain loop stability. The decreased of UGF is done by reducing the total gain while maintaining the dominant pole frequency. This technique has also further reduced the total quiescent current and improved the LDO’s efficiency. The proposed LDO exhibits low quiescent current 9.4μA and 17.7μA, at Iload zero and full load 100mA respectively. The supply voltage for this LDO is 1.2V with 200mV drop-out voltage. The design is validated using 0.13μm CMOS process technology.
Microcontroller-based camera with the sound source localization for automated accident detection Nur Nazifah Adlina Mohd Nazeem; Siti Lailatul Mohd Hassan; Ili Shairah Abdul Halim; Wan Fadzlida Hanim Abdullah; Nasri Sulaiman
International Journal of Advances in Applied Sciences Vol 13, No 3: September 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijaas.v13.i3.pp639-646

Abstract

This paper is on a microcontroller-based camera controller with sound source localization (SSL). With the rising frequency of highway accidents in Malaysia, there is a pressing need for a reliable detection system. The current approach, involving fixed-angled cameras, necessitates constant human monitoring, proving inefficient. To address this, the study introduces a hybrid camera system incorporating a camera for image capture and a microphone to detect collision sounds. By integrating a pan-tilt (PT) camera controller driven by time difference of arrival (TDOA) inputs, the system can swiftly move toward accident locations. The TDOA method is employed to convert sound arrival time differences into camera angles. The accuracy of the PT camera's rotation angle was analyzed based on the original sound source angle. As a result, this project produced an automated highway monitoring camera system that uses sound SSL to detect car crash sounds on highways. Its PT feature will help cover a large highway area and eliminate blind spots to capture possible accident scenes. The average inaccuracy of the experimental test of the pan and tilt angle of the camera is 19 and 23%, respectively. The accuracy of the pan tilt angle can be increased by adding more analog acoustic sensors.