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Xiaohui Fan
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Low Leakage Circuits Design with Optimized Gate-length Biasing Yangbo Wu; Xiaohui Fan; Haiyan Ni; Jianping Hu
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 4: April 2014
Publisher : Institute of Advanced Engineering and Science

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Abstract

With the technology process scaling, leakage power dissipation is becoming a growing number of percentage in total power dissipation. This study presents a new method in the gate-length biasing technique to achieve a cost-effective gate-length with a most benefit between leakage reduction and delay increasing. With the optimized gate-length, typical combinational and sequential circuits are realized and simulated using HSPICE with the BSIM4.6.4 predictive models at a 45nm COMS process. The results show that leakage currents of typical combinational circuits reduce more and delay increase less. Moreover, leakage currents of mirror adder and transmission gate adder decrease 13.9% and 8.90%, respectively; and leakage power of 4-bit binary counters using C2MOS D Flip-Flop and Transmission-Gate D Flip-Flop reduce 38.36% and 20.05%, with the frequency of 5M, respectively. Therefore, the optimized gate-length biasing technique is an attractive approach in low power circuits design. DOI : http://dx.doi.org/10.11591/telkomnika.v12i4.4791
Co-Authors Haiyan Ni Jianping Hu Yangbo Wu