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Z Zulfikar
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Computer Science & IT Control & Systems Engineering Electrical & Electronics Engineering Energy Engineering

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FPGA Implementation of Uniform Random Number based on Residue Method Z Zulfikar
Jurnal Rekayasa Elektrika Vol 11, No 1 (2014)
Publisher : Universitas Syiah Kuala

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (321.937 KB) | DOI: 10.17529/jre.v11i1.1990

Abstract

This paper presents the implementation and comparisons of uniform random number on Field Programable Gate Array (FPGA). Uniform random numbers are generated based on residue method. The circuit of generating uniform random number is presented in general view. The circuit is constructed from a multiplexer, a multiplier, buffers and some basic gates. FPGA implementation of the designed circuit has been done into various Xilinx chips. Simulation results are viewed clearly in the paper. Random numbers are generated based on different parameters. Comparisons upon occupied area and maximum frequency from different Xilinx chip are examined. Virtex 7 is the fastest chip and Virtex 4 is the best choice in terms of occupied area. Finally, Uniform random numbers have been generated successfully on FPGA using residue method.Keywords: FPGA implementation, random number, uniform random number, residue method, Xilinx chips
Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code Z Zulfikar
Jurnal Rekayasa Elektrika Vol 10, No 2 (2012)
Publisher : Universitas Syiah Kuala

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (353.274 KB) | DOI: 10.17529/jre.v10i2.116

Abstract

A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared. The VHDL code which limits range of integer values is occupies less area than the one which is not. This VHDL coding method is suitable for multi stage circuits.
FPGA Implementation of Uniform Random Number based on Residue Method Z Zulfikar
Jurnal Rekayasa Elektrika Vol 11, No 1 (2014)
Publisher : Universitas Syiah Kuala

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.17529/jre.v11i1.1990

Abstract

This paper presents the implementation and comparisons of uniform random number on Field Programable Gate Array (FPGA). Uniform random numbers are generated based on residue method. The circuit of generating uniform random number is presented in general view. The circuit is constructed from a multiplexer, a multiplier, buffers and some basic gates. FPGA implementation of the designed circuit has been done into various Xilinx chips. Simulation results are viewed clearly in the paper. Random numbers are generated based on different parameters. Comparisons upon occupied area and maximum frequency from different Xilinx chip are examined. Virtex 7 is the fastest chip and Virtex 4 is the best choice in terms of occupied area. Finally, Uniform random numbers have been generated successfully on FPGA using residue method.Keywords: FPGA implementation, random number, uniform random number, residue method, Xilinx chips
Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code Z Zulfikar
Jurnal Rekayasa Elektrika Vol 10, No 2 (2012)
Publisher : Universitas Syiah Kuala

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.17529/jre.v10i2.116

Abstract

A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared. The VHDL code which limits range of integer values is occupies less area than the one which is not. This VHDL coding method is suitable for multi stage circuits.
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