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Observation of Photovoltaic Effect and Single-photon Detection in Nanowire Silicon pn-junction Udhiarto, Arief; Purwiyanti, Sri; Moraru, Daniel; Mizuno, Takeshi; Tabe, Michiharu
Makara Journal of Technology
Publisher : UI Scholars Hub

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Abstract

We study nanowire silicon pin and pn-junctions at room and low temperature. Photovoltaic effects are observed for both devices at room temperature. At low temperature, nanowire pn-junction devices show their ability to detect single photon. This ability was not been observed for pin devices. Phosphorus-boron dopant cluster in the depletion region is considered to have the main role for single-photon detection capability. Fundamental mechanism of dopant-based single-photon detection in nanowire pn-junction is described in details.
Observation of Tunneling Effects in Lateral Nanowire pn Junctions Purwiyanti, Sri; Udhiarto, Arief; Moraru, Daniel; Mizuno, Takeshi; Hartanto, Djoko; Tabe, Michiharu
Makara Journal of Technology Vol. 18, No. 2
Publisher : UI Scholars Hub

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Abstract

As electronic device dimensions are continuously reduced, applied bias conditions significantly change and the transport mechanisms must be reconsidered. Tunneling devices are promising for scaled-down electronics because of expected high-speed operation and relatively low bias. In this work, we investigated the tunneling features in silicon-oninsulator lateral nanowire pn junction and pin junction devices. By controlling the substrate voltage, tunneling features can be observed in the electrical characteristics. We found that the minimum substrate voltage required for tunneling to occur in pn junctions is higher as compared with pin junctions. The main cause of these effects relies in the difference between the doping profiles, since the pn junctions contain a co-doped region, while the pin junctions contain an i-layer.
Fabrication of Organic Light Emitting Diodes (OLEDs) using the Lamination method in a Vacuum-Free Environment Alfafa, Daris; Moraru, Daniel; Udhiarto, Arief
International Journal of Electrical, Computer, and Biomedical Engineering Vol. 1 No. 2 (2023)
Publisher : Universitas Indonesia

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.62146/ijecbe.v1i2.24

Abstract

Organic Light Emitting Diodes (OLEDs) have recently become one of the fastest-growing technologies in the world. The challenge in OLED fabrication, especially larger-area OLEDs, is its relatively high costs and complexity. The lamination method at a vacuum-free environment is an approach to simplify and reduce the cost of fabrication. This paper reports our latest progress on OLEDs fabricated using the said method and condition. The processing parameters were explored and optimized. Spin coating the emissive Layer (PFO) at 1300 rpm and the anode (TC-07-S) at 3000 rpm yield the best results in terms of current conduction and success rate. Laminating the OLEDs at 160 °C, with 245 N of force, and for 30 seconds, gave the best results in terms of previously stated parameters. Furthermore, the constituting materials of the OLEDs were explored. It was found that TC-07-S as an anode, PFO as the light-emitting material, a 30-micrometer thick aluminum foil as the cathode, and Kapton as the dielectric and adhesive material yielded the best results. These results may pave the way for other innovative methods to fabricate OLEDs with a simple and affordable processes.
Challenges and Progress in the Fabrication of Silicon Nanowire Tunnel Diodes Moraru, Daniel
International Journal of Electrical, Computer, and Biomedical Engineering Vol. 1 No. 1 (2023)
Publisher : Universitas Indonesia

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.62146/ijecbe.v1i1.23

Abstract

Tunnel (Esaki) diodes prepared in silicon (Si) nanowires could provide a unique platform to investigate band-to-band tunneling (BTBT) transport in nanoscale. However, the successful fabrication of these devices poses substantial challenges, related to controlling high doping concentrations, maintaining the abruptness of the pn junction, and minimizing roughness due to nanoscale patterning. This paper comprehensively addresses these challenges, suggesting potential strategies for optimization. Additionally, examples of nanoscale diodes fabricated so far in silicon-on-insulator (SOI) substrates are showcased, highlighting their tunnel-diode characteristics at low temperatures. Furthermore, the underlying physics is discussed: phonon-assisted tunneling, single-charge tunneling and donor-acceptor compensation. For practical applications, such as photodetectors or tunnel field-effect transistors, room-temperature operation is also required.