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Cecilia Susilawati
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Electrical & Electronics Engineering

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ANALISIS NILAI RATA-RATA DARI SUATU MODEL JARINGAN ANTRIAN TERTUTUP Susilawati, Cecilia
Jurnal Teknik Elektro Vol 2, No 2 (2003)
Publisher : Jurnal Teknik Elektro

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Abstract

In a closed queueing network model it will use mean value analysis to determine the networkthroughput for different value of p, to find the value of p that gives maximum networkthroughput and to indicate the network bottleneck. For certain chosen values of parametersinvolved in this model, it found that the maximum network throughput is 288.1 for p=0.67.The network bottleneck is the fast server. For p>0.67 the fast server is also the networkbottleneck, but when p<0.67, the network bottleneck is the slow server.Keywords: throughput, server, job
ANALISA, PERANCANGAN DAN SIMULASI RANGKAIAN PEREDAM RC PASIF PADA PENYALURAN SEDERHANA SISTEM TENAGA DC DENGAN MENGGUNAKAN PSPICE Susilawati, Cecilia
Jurnal Teknik Elektro Vol 7, No 1 (2007)
Publisher : Jurnal Teknik Elektro

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The sub-system interaction and instability phenomena are a common problem in theDistributesd Power System (DPS). In order to regulate the output voltage or the speed, theinternal control function of a converter known as constant power load (CPL), results in theconverter tends to draw a constant power. This phenomena cause the input impedance ofCPL has negative incremental input impedance, which tends to create instability as it isconnected to a system. This paper concerns about the compensation method used to improvethe stability ot two or more connected subsystems, consisting of and L-C filter and a CPL. Acompensation method known as passive damping network containing only RC components isexamined purposedly to eliminate and reduce the instability of the subsystem. The passivedamping network was designed and simulated using PSpice. The results show that thedesigned passive damping network suitbale for small-scale power distribution system thatcontains constant power load with power level of 1kW.Keywords: Constant Power Load, DC – DC Converter, Passive Damping Circuit
PERANCANGAN MIXER UP-CONVERSION CMOS UNTUK RANGKAIAN RF TERINTEGRASI Susilawati, Cecilia
Jurnal Teknik Elektro Vol 8, No 1 (2008)
Publisher : Jurnal Teknik Elektro

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The design, analysis and implementation of a high frequency 1-3GHz tunable pure NMOSQuadrature Up-Conversion mixer topology are presented. The mixer is implemented in adeep submicron 0,25 μm CMOS process technology. Utilizing an off-chip tunable inductorachieves tunable range of frequency. Various passive components had been incorporated inits circuitry to increase the linearity of the topology. The mixer, which is a configuration of abalanced modulator, is composed from a Parallel Structure Low Voltage Multipliertopology, a High Gain Phase Shifting network and a Differential Cascade amplificationstage at the output. Various topology of four quadrant multiplier, biased in different regionof operation has been simulated and analyzed. The utilized topology requires fewer amountof stacked transistors, thus reducing the voltage headroom requirement of the circuitry. Theproposed high gain phase shifter relaxes the requirement of cascading several stages oflimiting amplifier at the output. Operating from a power supply of 2.0V, it consumes 150mWof power, with an OIP3 of 0dBm and 1dB compression level of 4.6dB.Keywords: Balanced Modulator, CMOS analog integrated circuit, Mixers, Phase shifters,RFIC
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