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All Journal TELKOMNIKA (Telecommunication Computing Electronics and Control) Indonesian Journal of Electrical Engineering and Computer Science
Yevgeniya Aitkhozhayeva
Satbayev University
Computer Science & IT

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Modular reduction with step-by-step using of several bits of the reducible number Sakhybay Tynymbayev; Yevgeniya Aitkhozhayeva; Dana Tananova; Sairan Adilbekkyzy
Indonesian Journal of Electrical Engineering and Computer Science Vol 25, No 2: February 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v25.i2.pp1087-1093

Abstract

Although public key cryptography is known to solve the problem of physically secure key exchange, the main drawback of this system is its low performance during encrypting and decrypting data. One of the ways to solve this issue is to increase the speed of the modular reduction operation, one of the basic operations of asymmetric cryptoalgorithms. A new method of step-by-step reduction by the N-bit module P using several bits of the 2Nbit reducible number A in one step is proposed in this paper. The method is based on using multiples of the P and reducing modulo at each step not the entire initial number, but its parts (A1, A2… Ai), which allows to reduce the bit capacity of A. A structural diagram of the hardware implementation of this method are developed. The main unit of the modular reduction device is a block of partial remainder formers, in which the partial remainder is computed using multiples of the P. The circuits are modeled in the Vivado Design Suite computer aided design (CAD) on base Artix-7 Fieldprogrammable gate array (FPGA) device from Xilinx. Optimization of hardware costs is achieved by applying the same comparison circuits to compare different multiples of P with Ai
High-speed dividing device with the formation of quotient and remainder Yevgeniya Aitkhozhayeva; Khalicha Yubuzova
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 23, No 4: August 2025
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v23i4.26306

Abstract

Considered the possibility of accelerating the time-critical operation of division for multi-bit integers. This problem is significant since, so multi-bit integers are widely used in specialized devices, including cryptographic transformations. A method for high-speed quotient and remainder determination with optimal hardware costs is proposed. A preliminary increase in the divisor and its subsequent decrease by shifting it to the right are used. A structural diagram and functional diagram of the hardware implementation have been developed using high-speed combinational logic circuits. The device’s principle of operation, its step-by-step process, and specific examples illustrating its correct operation and resource efficiency are addressed. On average, it takes (k/2+1) clock cycles to obtain the result, where (k+1) bit capacity of the quotient. In most division schemes with optimal hardware costs, the number of clock cycles required to obtain the quotient (without remainder) is (k+1). High-speed division with simultaneous determination of several quotient bits requires (m/p) clock cycles for the division operation, where p- the number of simultaneously determined quotient bits, m-bit capacity of dividend. However, this approach will require additional hardware. The research will continue by modeling the device in Vivado Design Suite computer aided design (CAD) based on Artix-7 field programmable gate array (FPGA) from Xilinx.
Co-Authors Dana Tananova Khalicha Yubuzova Sairan Adilbekkyzy Sakhybay Tynymbayev