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All Journal International Journal of Electrical and Computer Engineering Indonesian Journal of Electrical Engineering and Computer Science
Devendra Kumar Sharma
SRM Institute of Science and Technology
Computer Science & IT Electrical & Electronics Engineering

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Low power architecture of logic gates using adiabatic techniques Minakshi Sanadhya; Devendra Kumar Sharma
Indonesian Journal of Electrical Engineering and Computer Science Vol 25, No 2: February 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v25.i2.pp805-813

Abstract

The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips of very high density, has recently led to rapid and inventive progresses in low-power design. The most effective technique is adiabatic logic circuit design in energy-efficient hardware. This paper presents two adiabatic approaches for the design of low power circuits, modified positive feedback adiabatic logic (modified PFAL) and the other is direct current diode based positive feedback adiabatic logic (DC-DB PFAL). Logic gates are the preliminary components in any digital circuit design. By improving the performance of basic gates, one can improvise the whole system performance. In this paper proposed circuit design of the low power architecture of OR/NOR, AND/NAND, and XOR/XNOR gates are presented using the said approaches and their results are analyzed for powerdissipation, delay, power-delay-product and rise time and compared with the other adiabatic techniques along with the conventional complementary metal oxide semiconductor (CMOS) designs reported in the literature. It has been found that the designs with DC-DB PFAL technique outperform with the percentage improvement of 65% for NOR gate and 7% for NAND gate and 34% for XNOR gate over the modified PFAL techniques at 10 MHz respectively.
Adiabatic technique based low power synchronous counter design Minakshi Sanadhya; Devendra Kumar Sharma; Alfilh Raed Hameed Chyad
International Journal of Electrical and Computer Engineering (IJECE) Vol 13, No 4: August 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v13i4.pp3770-3777

Abstract

The performance of integrated circuits is evaluated by their design architecture, which ensures high reliability and optimizes energy. The majority of the system-level architectures consist of sequential circuits. Counters are fundamental blocks in numerous very large-scale integration (VLSI) applications. The T-flip-flop is an important block in synchronous counters, and its high-power consumption impacts the overall effectiveness of the system. This paper calculates the power dissipation (PD), power delay product (PDP), and latency of the presented T flip-flop. To create a 2-bit synchronous counter based on the novel T flip-flops, a performance matrix such as PD, latency, and PDP is analyzed. The analysis is carried out at 100 and 10 MHz frequencies with varying temperatures and operating voltages. It is observed that the presented counter design has a lesser power requirement and PDP compared to the existing counter architectures. The proposed T-flip-flop design at the 45 nm technology node shows an improvement of 30%, 76%, and 85% in latency, PD, and PDP respectively to the 180 nm node at 10 MHz frequency. Similarly, the proposed counter at the 45 nm technology node shows 96% and 97% improvement in power dissipation, delay, and PDP respectively compared to the 180 nm at 10 MHz frequency.
Co-Authors Alfilh Raed Hameed Chyad Minakshi Sanadhya