Claim Missing Document
Check
Articles

Found 2 Documents
Search

PROTOTYPE APPLICATION OF CROWD DETECTION SYSTEM FOR TRADITIONAL MARKET VISITOR BASED ON IOT USING RFID MFRC522 Wirmanto Suteddy; Dastin Aryo Atmanto; Rizki Nuriman; Afila Ansori
Jurnal Teknologi Informasi Universitas Lambung Mangkurat (JTIULM) Vol. 7 No. 1 (2022)
Publisher : Fakultas Teknik Universitas Lambung Mangkurat

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.20527/jtiulm.v7i1.117

Abstract

Crowds of people are the government's concern in dealing with the COVID-19 pandemic because the virus transfers unwittingly from one person to another and transmits it to the closest environment. One of the locations where crowds are difficult to avoid is a traditional market and is thought to be one of the places that have the potential to become the center of the spread of COVID-19. Various efforts made by the government in suppressing crowds have yielded results, but not a few violations that occur are carried out intentionally or unintentionally, one of the efforts to prevent crowd violations is the traditional market visitor detection monitoring system by market management so that market visitors do not violate health protocols and crowds that occur in an area can be avoided. In this study, an IoT-based crowd detection system application prototype uses an RFID sensor MFRC522 as a crowd indicator based on data on the number of visitors entering a kiosk that is recorded in the database and then displayed on the application, this data becomes an indicator of which kiosk other visitors want to go to so that the crowd can be avoided. System functionality testing was carried out with 4 scenarios and system reliability testing through data transmission was carried out 10 times with test data in the form of kiosk id and visitor id sent via a single Transmission Control Protocol (TCP) with a full-duplex communication channel. The test results show that crowd indications can be detected in the application with data transmission speeds reaching 875 KB/s with an average delay of 231.4 ms and a standard deviation of 215 ± 313 ms.
Fault Coverage Testing on the ISCAS’89 S1423 Sequential Circuit using Scan Based Design and Synopsis Tetramax Wirmanto Suteddy; Anugrah Adiwilaga; Dastin Aryo Atmanto
Journal of Computer Engineering, Electronics and Information Technology Vol 1, No 2 (2022): COELITE: Volume 1, Issue 2, 2022
Publisher : Universitas Pendidikan Indonesia

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (646.038 KB) | DOI: 10.17509/coelite.v1i2.43826

Abstract

We tested the ISCAS'89 S1423 series with a scan design method, both non-scan, full-scan, and partial-scan, but for the partial-scan, the method we propose uses a structured random approach. The purpose of this study is to determine the evaluation and performance with the best computational time with the proposed method to produce high fault coverage results. Testing the ISCAS'89 S1423 circuit in the form of verilog was carried out using tetramax synopsis, the partial-scan test requires a strategy in determining the flip flop to be used as a scannable flip flop, the test results using the full scan method produce 100% test coverage and fault coverage, but this method provides gate overhead loss of 24.06% and slower chip performance. To reduce the gate overhead loss, a partial-scan method will be applied with the approach of choosing from 74 DFF which will be used as scannable flip flops, the test with the best results we did through the 37 DFF approach with the highest input obtained test coverage of 98.17% and fault coverage 96.76% with 171.11 CPU Time with gate overhead reduced by 12.03%. The next approach with the best results with the approach of 50 DFF highest output plus DFF which is not self-loop obtained test coverage of 99.24% and fault coverage of 98.47% with gate overhead successfully reduced by 16.26% with CPU Time 43.39.