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Mohamed Syed Ali
AMET University

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Reconfigurable Modulation Scheme for Communication System Mohamed Syed Ali
Indonesian Journal of Electrical Engineering and Computer Science Vol 9, No 3: March 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v9.i3.pp624-628

Abstract

In any communication system transmitter and receiver are used to transmit the signal via wired or wireless channel. In the transmitter, modulation is one of the processes to transmit the signal efficiently. Likewise, receiver contains demodulation to recover the original signal from the transmitter. In general, the communication system uses one modulation/demodulation process at a time. It cannot use different modulation/demodulation within a single system. To overcome this problem reconfiguration technique is implemented. It is the method using different modulation scheme at the same time. It will increase the efficiency of the communication system. QPSK and BPSK modulation technique is used to transmit and receive the signal.
Cascaded Ripple Carry Adder Based SRCSA for Efficient FIR Filter Mohamed Syed Ali
Indonesian Journal of Electrical Engineering and Computer Science Vol 9, No 2: February 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v9.i2.pp253-256

Abstract

Filter is one of the key components of all signals processing elements. Both the FIR and IIR filter are used to reduce the unwanted signal in the original signal. Here discussing the FIR filter and design the efficient FIR filter using Dual Ripple Carry Adder (RCA) based SQRT-carry select adder (CSLA). Many components present in the FIR filter, one of the main component is Adder. Adder is used to combine the signal for avoid the noise occurring in the output. Proposed a Dual RCA based SQRT-CSLA for speed up the filtering process. The filter performance can be analyzed by Xilinx simulation environment.
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