Arres Bartil
Ferhat Abbas University

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Revealing and evaluating the influence of filters position in cascaded filter: application on the ECG de-noising performance disparity Abdenour Allali; Arres Bartil; Lahcene Ziet; Amar Hebibi
Indonesian Journal of Electrical Engineering and Computer Science Vol 21, No 2: February 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v21.i2.pp829-838

Abstract

In this paper, a new optimization on windowing technique based on finite impulse response (FIR) filters is proposed for revealing and evaluating the Influence of filters position in cascaded filter tested on the ECG signal de-noising. baseline wander (BLW), power line interference (PLI) and electromyography (EMG) noises are getting removed. The performance of the adopted method is evaluated on the PTB diagnostic database. Subsequently, the comparisons are based on signal to noise ratio (SNR) improvement and mean square error (MSE) minimization. Where the Rectangular, and Kaiser windows have been used for the more potent performances. The disparity average (DA) of SNR values is detected; in both Kaiser and Rectangular windows are assessed by ±0.38046dB and ±0.70278dB respectively, while the MSE values were constant. The excellent configuration or filters position (H-B-L) of the filtration system is selected according to high measurements of SNR and low MSE too, to de-noise the ECG signals. First of all, this applied approach has led to 31.30 dB SNR improvement with MSE minimization of 26. 43%. This means that there is a significant contribution to improving the field of filtration.
Comparison of two new methods for implementa BPSK modulator using FPGA Hebibi Amar; Arres Bartil; Lahcene Ziet
Indonesian Journal of Electrical Engineering and Computer Science Vol 19, No 2: August 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v19.i2.pp819-827

Abstract

The design of electronic systems has become mainly dependent on FPGAs applications. This is due to the softness effectiveness progress by reconfigurable computing and reduced time to develop solutions for digital signal processing. In this article, we present the theoretical backgrounds of a BPSK modulation and hardware designs of the BPSK system, a firstly with the help of Matlab/Simulink reliant on the System Generator and a second with Xilinx ISE VERILOG Hardware Description Language. In order to show the differences between them, in terms of efficiency, duration of development and how many resources are used in FPGA. For the projected system, we have a tendency to aimed toward employing a moderately sized, low-value FPGA to implement the system. The Atlys development board by Digilent to configure develops, and run the system, based on a Xilinx Spartan-6 LX45 FPGA.