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Ming-Yu Lin
National Yunlin Universityof Science and Technology

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Low Cost Quasi Binary Weighting Addition Log-SPA LDPC Decoders Po-Hui Yang; Ming-Yu Lin
Indonesian Journal of Electrical Engineering and Computer Science Vol 11, No 5: May 2013
Publisher : Institute of Advanced Engineering and Science

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Abstract

This paper proposes a new addition method, which can be applied to reduce the hardware cost of LDPC decoders using log-SPA, which traditionally has the best lowest bit error rate (BER) but the highest hardware requirement. The proposed quasi-binary weighting addition can be simply implemented by OR gates. With auxiliary pseudo-carry circuit, the BER performance can reach a fair level. In the log-SPA message-passing path, numeric transform reduction architecture is proposed for further hardware reduction. Synthesized and numerical results show that the new proposed architecture achieved an up to 32% and 18% total hardware reduction, compared with traditional log-SPA decoders, and the simplest sign-min architecture, respectively, with fair BER performance. DOI: http://dx.doi.org/10.11591/telkomnika.v11i5.2505
Co-Authors Po-Hui Yang