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N. Shylashree
RV College of Engineering

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Optimal path discovery for two moving sinks with a common junction in a wireless sensor network Satish Tunga; Sadashiva V. Chakrasali; N. Shylashree; Latha B. N.; Mamatha A. S.
Indonesian Journal of Electrical Engineering and Computer Science Vol 23, No 2: August 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v23.i2.pp879-889

Abstract

A new algorithm is described for determining the optimal round-trip paths for two moving sinks in a wireless sensor network. The algorithm uses binary integer programming to select two non-overlapping shortest paths except having a common junction node to cover all the sensor nodes. The two paths are balanced as nearly equal as possible. That is the sensor nodes along each path are equal or differ by just one depending on whether the total number of sensor nodes excluding the junction node is even or odd. In this method, both the path lengths are made equal or very nearly equal while the total length is minimized. This integrated approach is a novel and unique solution to solve the dual moving sink path problem in a wireless sensor network.
A novel design for hardware interface board with reduced resource utilization G. S. Ananth; N. Shylashree; Satish Tunga; Latha B. N.
Indonesian Journal of Electrical Engineering and Computer Science Vol 24, No 3: December 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v24.i3.pp1414-1420

Abstract

The final cost of an integrated circuit (IC) is proportional to its testing time. One of the main goals of test engineers when building an IC test solution is to reduce test time. Reduction of Test time is achieved by multi-site testing where multiple ICs are tested simultaneously using automated test equipment (ATE). During multi-site testing, if a certain test requires abundant resources, it is accomplished by testing one set of ICs at a time while the other ICs remain idle, thus lengthening the total test time. In digital-analog hybrid ICs, both analog and digital tests need to be performed, increasing the tester resource requirement and causing digital resource shortage. This paper describes a hardware interface board (HIB) design for a test case of a digital-analog IC on Teradyne’s ETS-364 ATE. The HIB's design allows the ATE to perform multi-site I2C based tests, which usually require lot of tester resources, utilizing only two digital resources and one measurement resource. This design achieves halving the I2C test time while lowering the number of resources necessary for multi-site testing compared to set-by-set testing. The proposed work has achieved up to 90.625% of resource reduction for multisite testing for a single test.
Co-Authors G. S. Ananth Latha B. N. Mamatha A. S. Sadashiva V. Chakrasali Satish Tunga Satish Tunga