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Yang Huijing
Harbin University of Science and Technology

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A High Performance Sigma-Delta ADC for Audio Decoder Chip Yu Fan; Yang Huijing; Li Gang
Indonesian Journal of Electrical Engineering and Computer Science Vol 11, No 11: November 2013
Publisher : Institute of Advanced Engineering and Science

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Abstract

This paper gives a high performance sigma delta Analog to Digital Converter (ADC) applied in computer audio decoder chip. In this design, a 3rd-order single-loop CIFF topology is chosen to achieve the high performance ADC. Its signal bandwidth is 20KHz, sampling frequency is 10.24MHz and oversampling ratio is 256. Local feedback coefficient is used to reduce quantization noise. The non-linear model of modulator is given and the stability is analyzed. It is got that when quantizer gain is bigger than 0.322 the system is stable. According to simulation, Signal to Noise Ratio (SNR) is 123.1dB and Effective Number of Bits (ENOB) is 20.15bits. When input level is bigger than -3dBFs, the modulator is overload and becomes unstable. Then the integrator, quantizer and feed forward summation in ADC circuit are designed.  Then the ADC is implemented in 0.6um CMOS process, and the test result shows that its performance is 99.28dB. DOI: http://dx.doi.org/10.11591/telkomnika.v11i11.3498
A 4th-order Switch-capacitor Low-pass Filter for Quartz Gyroscope Interface Circuit Yu Fan; Yang Huijing; Li Gang
Indonesian Journal of Electrical Engineering and Computer Science Vol 11, No 10: October 2013
Publisher : Institute of Advanced Engineering and Science

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This paper presents the computer aided design of a 4th-order switch-capacitor low-pass filter applied in quartz gyroscope interface circuit. After a introduction of switch-capacitor filter (SCF) and its application in quartz gyroscope, the system-level analysis and design is given. Then the circuit design of amplifier, CMOS switch and non-overlapping clock is described. The Fourth-order low-pass SCF has been implemented under 0.5um CMOS process and simulated in computer aided design software. The final simulation results show that the passband is 99.7Hz , and the maximum pass-band ripple is about 0.14dB.The stop-band is 1KHz, and the minimum stop-band attenuation is 78.6dB. DOI: http://dx.doi.org/10.11591/telkomnika.v11i10.3398  
Efficient Implementation of Decimal Floating Point Adder in FPGA Yang Huijing; Yu Fan; Han Dandan
Indonesian Journal of Electrical Engineering and Computer Science Vol 11, No 10: October 2013
Publisher : Institute of Advanced Engineering and Science

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Decimal floating Point adder is one of the most frequent operations used by many financial, business and user-oriented applications but current implementations in FPGAs are very inefficient in terms of both area and latency when compared to binary floating point adder. This paper has shown an efficient implementation of a new parallel decimal floating point module on a reconfigurable platform, which is both area as well as performance optimal. The decimal floating-point Adder was further pipelined into five stages to increase the maximum frequency of operation. The synthesis results for a Stratix IV device indicate that our implementations have 25.1% reduction of the latency and 1.1% reduction of area compared to an existing alter-core adder design, presenting area and delay figures close to those of optimal binary adder trees. DOI: http://dx.doi.org/10.11591/telkomnika.v11i10.3406 
Co-Authors Han Dandan Li Gang Yu Fan