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All Journal Indonesian Journal of Electrical Engineering and Computer Science
M.N.Mohd Warip
University Malaysia Perlis

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Performances analysis of reducing router in ring and mesh topology for network-on-chip (NoC) architecture Ng Yen Phing; M.N.Mohd Warip; Phaklen Ehkan; R Badlishah Ahmad; F.W. Zulkefli
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp802-809

Abstract

The size of the transistor has reached physical processor limitation in particular for traditional bus-based and point-to-point architecture in system-on-chip (SoC). Therefore, network-on-chip (NoC) was proposed as a solution. The performances required for the optimization of the NoC are low network latency, low power consumption, small area, and high throughput. However, recently the size of the NoC architecture has increased and the communication between cores to core become complicated. To overcome this disadvantages, topology plays an important role. In this paper, we reduce the number of the router in the 16 cores and 64 cores ring and mesh topologies by connected more numbers of node in each router. Result shows that reducing the number of the router in 64 cores ring topology outperforms the conventional topologies in term of area, power consumption, latency, and accepted packet rate. Reducing router in 64 cores ring topology decrease the average area, power consumption, latency, and increase the average accepted packet rate by 160.45%, 23.88%, 54.76%, and 223.88% over the 64 cores mesh, reducing router in mesh, ring, and cross-link mesh topologies.
Co-Authors F.W. Zulkefli Ng Yen Phing Phaklen Ehkan R Badlishah Ahmad