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Jyotirmoy Sil Sharma
Tripura University

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Regular clocking scheme based design of cost-efficient comparator in QCA Jayanta Pal; Mojtaba Noorallahzadeh; Jyotirmoy Sil Sharma; Dhrubajyoti Bhowmik; Apu Kumar Saha; Bibhash Sen
Indonesian Journal of Electrical Engineering and Computer Science Vol 21, No 1: January 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v21.i1.pp44-55

Abstract

Quantum-dot cellular automata (QCA) gained a notable attraction in the emerging nanotechnology to get the better of power consumption, density, nano-scale design, the performance of the present CMOS technology. Many designs had been proposed in QCA for an arithmetic circuit like adder, divider, parity checker and comparator etc. Most of the designs have been facing the challenges of cost efficiency, power dissi-pation, device density etc. However, consideration of design automation, underlying clocking layout and integration of the sub modules are the most important which has a direct impact on the fabrication of the design. This work proposed a novel cost ef-fective and power aware comparator design, which is an essential segment in central processing unit (CPU). The noticeable novelty of the design was the use of underlying regular clocking scheme. A new scalable, regular clocking scheme has been utilized in the coplanar design of the comparator which enables regular or uniform cell layout of QCA circuit. It also exhibited the significant improvement over existing counterparts having irregular clocking in terms of area and latency. QCADesigner was used to test and verify the functionality of the circuit and by using QCAPro the power dissipation has been analyzed.
Co-Authors Apu Kumar Saha Bibhash Sen Dhrubajyoti Bhowmik Jayanta Pal Mojtaba Noorallahzadeh