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All Journal International Journal of Electrical and Computer Engineering International Journal of Reconfigurable and Embedded Systems (IJRES)
Galiveeti Umamaheswara Reddy
Sri Venkateswara University
Computer Science & IT Economics, Econometrics & Finance Electrical & Electronics Engineering

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Delay-efficient 4:3 counter design using two-bit reordering circuit for high-speed Wallace tree multiplier Madaka Venkata Subbaiah; Galiveeti Umamaheswara Reddy
International Journal of Electrical and Computer Engineering (IJECE) Vol 13, No 2: April 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v13i2.pp1367-1378

Abstract

In many signal processing applications, multiplier is an important functional block that plays a crucial role in computation. It is always a challenging task to design the delay optimized multiplier at the system level. A new and delay-efficient structure for the 4:3 counter is proposed by making use of a two-bit reordering circuit. The proposed 4:3 counter along with the 7:3 counter, full adder (FA), and half adder (HA) circuits are employed in the design of delay-efficient 8-bit and 16-bit Wallace tree multipliers (WTMs). Using Xilinx Vivado 2017.2, the designed circuits are simulated and synthesized by targeting the device ‘xc7s50fgga484-1’ of Spartan 7 family. Further, in terms of lookup table (LUT) count, critical path delay (CPD), total on-chip power, and power-delay-product (PDP), the performance of the proposed multiplier circuit is compared with the existing multipliers.
Design and implementation of a novel approximate carry look ahead adder for low-power FIR filter applications Badiganchela Shiva Kumar; Galiveeti Umamaheswara Reddy
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 1: March 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i1.pp248-258

Abstract

Approximate computing is a low-power circuit design strategy that trades off computational accuracy for gains in speed, power efficiency, and area reduction. This approach achieves considerable power and area efficiency by introducing acceptable errors. The acceptable error in computation systems refers to a loss in accuracy that does not affect overall system performance. Approximate computing is mainly suitable for multimedia and signal processing applications. In this work, a novel approximate carry look-ahead adder (CLA) based on logical level modification is proposed. The new carry prediction term is derived to reduce the overall propagation delay of the addition operation. The proposed multi-bit adder design uses a square root based division method to partition the adder stages. Moreover, the proposed adder is applied in finite impulse response (FIR) filter implementation to evaluate the performance in real-time applications. The proposed adder and FIR filter are coded in Verilog and verified using the Xilinx simulator. The result shows that the proposed FIR filter achieves better results in terms of all parameters.
Co-Authors Badiganchela Shiva Kumar Madaka Venkata Subbaiah