Saher A. Albatran
Jordan University of Science and Technology

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A synchronization technique for single-phase grid applications Issam A. Smadi; Saher A. Albatran; Taher Q. Ababneh
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 13, No 4: December 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijpeds.v13.i4.pp2181-2189

Abstract

The utility grid disturbances like dc offset and harmonic components can severely affect the estimated variables from the phase-locked loop (PLL), resulting in poor performance of the system relying on it. Therefore, there is an emerging need for well-designed PLL algorithms ensuring robust response against different operating conditions. This paper proposes a simple single-phase PLL algorithm with inherent dc offset and specific harmonic orders rejection capability. Utilizing adaptive time-delay fictitious signal generation. A full mathematical model of the proposed PLL has been provided. The proposed PLL is compared with other filter-based single-phase PLLs, to validate its simplicity and excellent performance.