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All Journal Indonesian Journal of Electrical Engineering and Computer Science
Sasikumar Asaithambi
SRM Institute of Science and Technology

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A low-power high speed full adder cell using carbon nanotube field effect transistors Ramakrishna Reddy Eamani; Vinodhkumar Nallathambi; Sasikumar Asaithambi
Indonesian Journal of Electrical Engineering and Computer Science Vol 31, No 1: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v31.i1.pp134-142

Abstract

The adder circuit is basic component of arithmetic logic design and that is the most important block of processor architecture. Moreover, power consumption is the main concern for real-time digital systems. In recent times, carbon nanotube field effect transistors (CNTFET) used for arithmetic circuit designs with high performance. A creative substitute for highspeed, less power, and small size in area designs is the CNTFET. This paper presents 1- bit full adder with CNTFETs for low power and high performance. Using the computer aided design (CAD) tool the proposed 1-bit full adder design model is simulated using 32 nm with CNTFET technology, a voltage supply of +0.9V. Performance comparisons between various proposed designs and existing 1-bit full adder design have been made in terms of the delay, power, and power delay product (PDP). The proposed CNFET logic also design for n-bit carry look adder (CLA) and compare it to other CLAs to evaluate performance and reliability. The simulation results shows that the proposed adder consume less power than existing adders.
Co-Authors Ramakrishna Reddy Eamani Vinodhkumar Nallathambi