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All Journal Emerging Science Journal
Seyed Javad Azhari, Seyed Javad
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Environmental Science

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An Offset-free High linear Low Power High Speed Four-Quadrant MTL Multiplier Jafari, HoseinAli; Abbasi, Zahra; Azhari, Seyed Javad
Emerging Science Journal Vol 1, No 3 (2017): October
Publisher : Ital Publication

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (736.215 KB) | DOI: 10.28991/ijse-01115

Abstract

In this paper a new CMOS current-mode four-quadrant analog multiplier circuit is proposed. The major advantages of this design are high linearity, high speed and low power consumption. Removing dc offset is the most important improvement in this topology. The circuit is designed with 1.8V supply voltage and is simulated using HSPICE simulator by level 49 parameters in 0.18µm standard CMOS TSMC technology. The aspect ratios of the MOSFETs are optimized using Evolutionary algorithm by MATLAB. The simulation results of this analog multiplier demonstrate a maximum linearity error of 2.6%, a THD of 1.77%, maximum power consumption of 157 µW, -3dB bandwidth of 241MHz and almost free from dc offset.
A Novel Fully Differential Second Generation Current Conveyor and Its Application as a Very High CMRR Instrumentation Amplifier Ahmadi, Soma; Azhari, Seyed Javad
Emerging Science Journal Vol 2, No 2 (2018): April
Publisher : Ital Publication

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (975.104 KB) | DOI: 10.28991/esj-2018-01131

Abstract

This paper aims to introduce a novel Fully Differential second generation Current Conveyor (FDCCII) and its application to design a novel Low Power (LP), very high CMRR, and wide bandwidth (BW) Current Mode Instrumentation Amplifier (CMIA). In the proposed application, CMRR, as the most important feature, has been greatly improved by using both common mode feed forward (CMFF) and common mode feedback (CMFB) techniques, which are verified by a perfect circuit analysis. As another unique quality, it neither needs well-matched active blocks nor matched resistors but inherently improves CMRR, BW, and power consumption hence gains an excellent matchless choice for integration. The FDCCII has been designed using 0.18 um TSMC CMOS Technology with ±1.2 V supply voltages. The simulation of the proposed FDCCII and CMIA have been done in HSPICE LEVEL 49. Simulation results for the proposed CMIA are as follow: Voltage CMRR of 216 dB, voltage CMRR BW of 300 Hz. Intrinsic resistance of X-terminals is only 45 Ω and the power dissipation is 383.4 μW.  Most favourably, it shows a constant differential voltage gain BW of 18.1 MHz for variable gains (here ranging from 0 dB to 45.7 dB for example) removing the bottleneck of constant gain-BW product of Voltage mode circuits.
Co-Authors Ahmadi, Soma HoseinAli Jafari, HoseinAli Zahra Abbasi, Zahra