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Implementasi Transformasi Wavelet Diskret Haar pada FPGA Xilinx Spartan-3E Sasmito Aji
Jurnal Nasional Teknik Elektro dan Teknologi Informasi Vol 3 No 4: November 2014
Publisher : Departemen Teknik Elektro dan Teknologi Informasi, Fakultas Teknik, Universitas Gadjah Mada

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Abstract

This paper discusses the efficient and accurate implementation of the discrete Haar Wavelet Transform (HWT) by selection of the best fit filter bank structure and data format. There are three filter bank structures including one polyphase and two lattice filter bank structure and also three data formats including two fixed point and one single precision floating point data format which are used in implementation of discrete Haar wavelet transform are discussed in relation with the using of FPGA resources. Beside that this paper also discuss about the effect of decomposition level on utilization of FPGA resources. The decomposition level is varied from 1st to 6th level and then its effect on the FPGA resources will be observed. The implementation of the Haar wavelet transform is performed on Field Programmable Gate Array (FPGA) Xilinx Spartan-3E and it is intended for processing of voice signals. By using the lattice filter bank structure and fixed-point data format, the implementation of Haar Wavelet Transform with six decomposition levels only require 5% of FPGA’s slice and give accuracy 98.9%.
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