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All Journal International Journal of Power Electronics and Drive Systems (IJPEDS) TELKOMNIKA (Telecommunication Computing Electronics and Control)
Anass Mansouri
Sidi Mohamed Ben Abdellah University
Computer Science & IT Control & Systems Engineering Electrical & Electronics Engineering

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Dual-mode model predictive control for non-minimum phase boost converters Jawhra El Hmidi; Anass Mansouri; Ali Ahaitouf
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 17, No 2: June 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijpeds.v17.i2.pp1211-1220

Abstract

This paper aims to develop an efficient finite-set model predictive control (FS-MPC) strategy for DC-DC boost converters to improve voltage regulation while reducing computational complexity. The proposed approach introduces a split cost function that decouples voltage and current regulation, providing a simpler alternative to conventional long-horizon FS-MPC schemes used to address the converter’s non-minimum-phase (NMP) behavior. A current estimation technique is incorporated to eliminate the need for additional sensors, lowering hardware cost and improving robustness. Unlike existing FS-MPC methods that rely on horizon extension or extra measurements, the proposed strategy leverages the split cost structure to achieve comparable NMP compensation with significantly lower computational effort. The controller is implemented in real time using a hardware-in-the-loop (HIL) setup on a ZedBoard platform, with accurate data acquisition provided by an external ADC. Experimental results demonstrate that the proposed approach enhances voltage-tracking performance, eliminates overshoot and undershoot, reduces settling time by over 40%, and decreases computational effort by more than 80% compared to traditional FS-MPC methods.
Parallel field programmable gate array implementation of the sum of absolute differences algorithm used in the stereoscopic system Mohamed Sejai; Anass Mansouri; Saad Bennani Dosse; Yassine Ruichek
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 20, No 6: December 2022
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v20i6.22852

Abstract

Stereo vision is a popular method for an artificial vision-based environment perception system used in various applications such as intelligent transportation. With two cameras, the disparity map is calculated to find the distance and depth of objects in front of a moving vehicle. The key element of the stereoscopic system is based on the sum of absolute differences (SAD) algorithm, which is the most repeated operation in the stereo matching subsystem; however, this algorithm requires a very intensive processing time, statistical analysis show that the SAD block can consume more than 80% of the overall processing time of the algorithm. In this paper we propose a highly efficient hardware architecture of the SAD algorithm for real time stereo matching, the proposed architecture is established by a hierarchical parallel architecture of the SAD block, and verified by simulation and successfully implemented in Cyclone IV field programmable gate array (FPGA), it provides a significant reduction of processing time and the performance of the stereo imaging system is able to achieve 30 frames per second of 640×480 resolution color images.
Co-Authors Ali Ahaitouf Jawhra El Hmidi Mohamed Sejai Saad Bennani Dosse Yassine Ruichek