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All Journal International Journal of Electrical and Computer Engineering IAES International Journal of Artificial Intelligence (IJ-AI)
Venkatesh, Divyashree Yamadur
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Computer Science & IT Electrical & Electronics Engineering Engineering

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An efficient reconfigurable code rate cooperative low-density parity check codes for gigabits wide code encoder/decoder operations Venkatesh, Divyashree Yamadur; Mallikarjunaiah, Komala; Srikantaswamy, Mallikarjunaswamy
International Journal of Electrical and Computer Engineering (IJECE) Vol 13, No 6: December 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v13i6.pp6369-6377

Abstract

In recent days, extensive digital communication process has been performed. Due to this phenomenon, a proper maintenance of authentication, communication without any overhead such as signal attenuation code rate fluctuations during digital communication process can be minimized and optimized by adopting parallel encoder and decoder operations. To overcome the above-mentioned drawbacks by using proposed reconfigurable code rate cooperative (RCRC) and low-density parity check (LDPC) method. The proposed RCRC-LDPC is capable to operate over gigabits/sec data and it effectively performs linear encoding, dual diagonal form, widens the range of code rate and optimal degree distribution of LDPC mother code. The proposed method optimize the transmission rate and it is capable to operate on 0.98 code rate. It is the highest upper bounded code rate as compared to the existing methods. The proposed method optimizes the transmission rate and is capable to operate on a 0.98 code rate. It is the highest upper bounded code rate as compared to the existing methods. the proposed method's implementation has been carried out using MATLAB and as per the simulation result, the proposed method is capable of reaching a throughput efficiency greater than 8.2 (1.9) gigabits per second with a clock frequency of 160 MHz.
Efficient reconfigurable parallel switching for low-density parity-check encoding and decoding Venkatesh, Divyashree Yamadur; Mallikarjunaiah, Komala; Srikantaswamy, Mallikarjunaswamy
IAES International Journal of Artificial Intelligence (IJ-AI) Vol 14, No 1: February 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijai.v14.i1.pp260-269

Abstract

In the evolution of next-generation communication systems, the demand for higher data integrity and transmission efficiency has brought low-density parity-check (LDPC) codes into focus, particularly for their error-correcting prowess. Traditional LDPC encoding and decoding techniques, such as the belief propagation (BP), Min-Sum, and Sum-Product algorithms, are hampered by high computational complexity and latency. Our research introduces a groundbreaking approach: an efficient, reconfigurable highspeed parallel switching operation for a complexity-optimized low-density parity-check encoding and decoding model (CoLDPC-EC). This method leverages advanced parallel processing and reconfigurable computing to drastically enhance operational speed and efficiency. It significantly outperforms conventional algorithms by optimizing key parameters like decoding throughput and power consumption, ensuring swift, energy-efficient error correction ideal for cutting-edge communication technologies. Our comparison with traditional methods underscores our solution's superior speed, flexibility, and efficiency, promising a leap forward in reliable, highspeed data transmission for next-generation networks. As per the simulation analysis, the proposed system shows better performance compared to conventional methods by 10.35%, 3.56%, and 2.36% in terms of decoding throughput, power consumption, and energy efficiency error correction, respectively.
Co-Authors Mallikarjunaiah, Komala Srikantaswamy, Mallikarjunaswamy