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Gadige, Aswini Kumar
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Computer Science & IT Electrical & Electronics Engineering

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Improvement of Philips MOS model 9 radio frequency performance with circuit level parasitic compensation Gadige, Aswini Kumar; Paremesha, Paremesha
International Journal of Electrical and Computer Engineering (IJECE) Vol 14, No 5: October 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v14i5.pp4977-4986

Abstract

The two circuit-level parasitic compensation techniques for the Philips metal oxide semiconductor (MOS) model 9 metal oxide semiconductor field effect transistor (MOSFET) at high frequencies (in the GHz range) are presented in this paper. The first method involves connecting the series resonant LC circuit in parallel to the drain and grounded source/bulk of the MM9; the second method involves connecting two of these MM9s in parallel to increase the drain current at higher frequencies along with parasitic compensation. Using these compensatory techniques, it is possible to reduce the impact of drain-source parasitic capacitance on MOS model 9 by preventing the short circuit of MOSFET terminals at high frequencies. After adjustment, improvements were seen in a number of metrics, including output impedance, S-parameters, output power and stability. Finally, using a 10 dBm source power, these parasitic compensation techniques are applied to a single and two stage basic class-E power amplifier and simulated at 1.7 and 1.1 GHz, respectively. Improvements are noted in multiple performance parameters, including power Gain (16.5 dB), drain Efficiency (83%), power added efficiency (85.82%), output power (26 dBm), good Stability (K=2.23, B>0), and S-parameters (S11=-9.22 dB, S12=-39.78 dB, S21=16.38 dB, and S22=1.41 dB) in two-stage cascade power amplifier.
Co-Authors Paremesha, Paremesha