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All Journal International Journal of Electrical and Computer Engineering International Journal of Power Electronics and Drive Systems (IJPEDS)
Prathap, Joseph Anthony
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Computer Science & IT Control & Systems Engineering Electrical & Electronics Engineering

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Design of decryption process for advanced encryption standard algorithm in system-on-chip Prathap, Joseph Anthony; Raj, Mrinal; Patnaik, Ritu
International Journal of Electrical and Computer Engineering (IJECE) Vol 14, No 6: December 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v14i6.pp6838-6845

Abstract

This paper concentrates on the development of system-on-chip for the decryption algorithm in the advanced encryption standard (AES). This method includes the transformation of cipher text into plain text and consists of 4 sub-tasks based on the resolution. In this work, the 128-bit resolution is utilized to perform 10 rounds of transformation with the round key added at every round generated by the key expansion algorithm. Though there are many cryptography algorithms, the AES is simple, secure, faster in operation, and easy to develop compared to the others. The system-on-chip (SOC) design for the decryption of the AES depends on the synthesizable hardware description language (HDL) code development for all 10 rounds of processes with the key expansion algorithm. The lookup tables (LUTs) are used for the inverse S-box in the HDL code. The proposed SOC is designed using the Cadence electronic design automation (EDA) tools by making use of the synthesized HDL code for the proposed methods and analyzed for the very large-scale integration (VLSI) parameters.
System-on-chip design for improved switching angle driven 35-level LUO progression-based multi-level inverter Prathap, Joseph Anthony; Prasad, J. Kanti; Reddy, Vivekananda; Suheil, Chinthapalli
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 16, No 2: June 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijpeds.v16.i2.pp974-981

Abstract

This article concentrates on the development of the IC layout for the driving switches of the inverter with improved switching control. This work uses the improved non-carrier switching pattern algorithms to have precise control of inverter switches with twin objectives of i) reducing the total harmonic distortion (THD)% and ii) developing a dedicated system on chip for the improved switching control of the 35-level switched ladder multi-level inverter. The DC voltage of the inputs to the inverter is designated based on the LUO progression, which consists of an improved mathematical formula for deriving its values. Conventionally, the multi-level inverter circuits are driven by the pulse width modulation signals by overlapping the modulating sine wave with different levels of triangle waves, such as phase disposition, phase opposite disposition, and alternate phase opposite disposition, utilized to drive various voltage source inverter topologies. Although the MLI design concentrates on minimal THD%, factors like accuracy, minimum number of switches, and cost demands for advanced switching strategy algorithms. This paper compares the improved switching angle method to the existing algorithm by considering VPEAK, VRMS, and %THD for the 35-level LUO progression-based switched ladder inverter. The IC layout for the improved switching control is developed using the hardware description language code in the Cadence tool and validated by cross-compiling in Simulink MATLAB.
Co-Authors Patnaik, Ritu Prasad, J. Kanti Raj, Mrinal Reddy, Vivekananda Suheil, Chinthapalli