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All Journal International Journal of Electrical and Computer Engineering
Zghoul, Fadi Nessir
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Computer Science & IT Electrical & Electronics Engineering

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An 8-bit successive-approximation register analog-to-digital converter operating at 125 kS/s with enhanced comparator in 180 nm CMOS technology Zghoul, Fadi Nessir; Al-Bakrawi, Yousra Hussein; Etier, Issa; Kannan, Nithiyananthan
International Journal of Electrical and Computer Engineering (IJECE) Vol 14, No 4: August 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v14i4.pp3830-3854

Abstract

Data converters are necessary for the conversion process of analog and digital signals. Successive approximation register (SAR) analog-to-digital converters (ADC) can achieve high levels of accuracy while consuming relatively low amounts of power and operating at relatively high speeds. This paper describes a design of 8-bit 125 kS/s SAR ADC with a proposed high-speed comparator design based on dynamic latch architecture. The proposed design of the comparator enhances the performance compared to a conventional dynamic comparator by adding two parallel clocked input complementary metal-oxide semiconductor (CMOS) transistors which reduce the parasitic resistance in the latch ground path and serve to minimize the latch delay time. The design of each sub-system for the ADC is explained thoroughly, which contains a sample and hold circuit, successive approximation register, charge redistribution types digital-to-analog converter, and the new proposed comparator. The proposed design is implemented using 180 nm CMOS technology with a power supply of 1.2 V. The average inaccuracy in differential non-linearity (DNL) is +0.6/−0.8 LSB (least significant bit), and integral non-linearity (INL) is +0.4/−0.7 LSB. The proposed design exhibits a delay time of 157 ps at 1 MHz clock frequency.
Optimizing power consumption in novel electrical design for single ended comparator circuit Zghoul, Fadi Nessir; Migdadi, Wafaa; Al-Mistarihi, Mamoun
International Journal of Electrical and Computer Engineering (IJECE) Vol 15, No 1: February 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v15i1.pp208-223

Abstract

Contemporary society electronic technology has evolved into a pivotal component across various facets of our lives. Its indispensability is particularly evident in the advancement of medical, agricultural, industrial, and other sectors. As this technology continues to play a crucial role, optimizing its performance in terms of speed, accuracy, and energy consumption becomes paramount. This paper introduces a novel electrical design for the threshold inverter quantization comparator circuit aiming to meet the evolving demands of modern electronic applications. The proposed design enhances the classic threshold inverter quantization comparator’s performance by significantly reducing its power consumption. Through rigorous mathematical analysis and simulation results it is demonstrated that the proposed comparator design achieves a remarkable 50% reduction in power consumption compared to the conventional threshold inverter quantization comparator. Subsequently the newly devised design is applied to the construction of a 4-bit flash analog-to-digital converter using 0.35 μm complementary metal–oxide–semiconductor (CMOS) technology.
Co-Authors Al-Bakrawi, Yousra Hussein Al-Mistarihi, Mamoun Etier, Issa Kannan, Nithiyananthan Migdadi, Wafaa