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All Journal International Journal of Electrical and Computer Engineering International Journal of Power Electronics and Drive Systems (IJPEDS)
Liu, Tian-Hua
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Computer Science & IT Control & Systems Engineering Electrical & Electronics Engineering

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Predictive controllers for synchronous reluctance motor drive systems Mubarok, Muhammad Syahril; B., Nur Vidia Laksmi; Liu, Tian-Hua
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 15, No 1: March 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijpeds.v15.i1.pp98-108

Abstract

This paper proposes the design and implementation of predictive controllers for synchronous reluctance motor drive systems to enhance their dynamic responses. The predictive speed and current controllers in this paper are designed in systematic procedures. The predictive speed controller is implemented by using Laguerre function procedure. The Laguerre function is used to simplify the algorithm and to minimize the execution time of the digital signal processor. For predictive current controller, a finite control set method improves the current tracking ability. The measured currents are used to predict the future phase-current based on the motor model. The optimal control inputs of both predictive controllers are determined by using a cost function minimization method. Experimental results show the proposed drive system provides a wide adjustable speed range, from 2 r/min to 1800 r/min. It has better performance than a proportional-integral (PI) controller including fast rise time, which is 0.9 second, small steady state error, which is 0.32 r/min, and small current ripples. A 32-bit floating-point digital signal processor, TMS-320-F-28335 DSP, is employed to implement the control algorithms.
Cascaded AC-DC parallel boost-flyback converter for power factor correction Laksmi B., Nur Vidia; Mubarok, Muhammad Syahril; Effendi, Moh. Zaenal; Aribowo, Widi; Liu, Tian-Hua
International Journal of Electrical and Computer Engineering (IJECE) Vol 15, No 1: February 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v15i1.pp224-234

Abstract

A two-stage power factor correction (PFC) topology achieves a higher power factor quality and lower harmonic distortion than a single-stage converter. This paper introduces a two-stage PFC topology using a parallel boost and flyback converter which is employed as a voltage regulator The main boost converter is used for PFC and the other is the active filter circuit. The filter is implemented to improve the quality of phase-current and eliminate the switching loss. Furthermore, a reaction curve of Ziegler-Nichol’s method determines the controller parameter for cascaded PFC converter circuit. Simulated and experimental results are presented to validate the proposed method. The total harmonic distortion (THD) value decreases significantly from 83.35% become 0.98% in the simulation. In addition, experimental results show that the current response has good performances, including less harmonics, higher power factor, and lower THD value compared to without a PFC circuit. The PF increased from 0.43 become 0.96, the THD value decreased from 49.4% become 16.2%, and contains a small number of harmonics. The proposed controller method has better responses than the conventional one, including small steady-state error, fast rise time and settling time. A microcontroller (MCU), type STM32F407VG, produced by STMicroelectronics is used to execute the proposed control in both converters.
Co-Authors Effendi, Moh. Zaenal Mubarok, Muhammad Syahril Nur Vidia Laksmi B Widi Aribowo