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All Journal International Journal of Power Electronics and Drive Systems (IJPEDS)
Sannasy, Balarajan
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Control & Systems Engineering Electrical & Electronics Engineering

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Fast synchronization with enhanced switching control for grid-tied single-phase square wave inverter using FPGA Sithananthan, Tharnisha; Bakar, Afarulrazi Abu; Sannasy, Balarajan; Utomo, Wahyu Mulyo; Taufik, Taufik
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 15, No 2: June 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijpeds.v15.i2.pp1105-1116

Abstract

Research on grid synchronization has been conducted worldwide by researchers in conjunction with the development of innovative technologies, such as dedicated short-range communication (DSRC) and cellular vehicle-to-everything (C-V2X). However, grid-connected inverters face several challenges, mainly the mismatch in voltage amplitude, frequency, and phase angle, as well as grid voltage disturbance and grid faults. Thus, the control algorithm of this research mainly focused on a half-cycle algorithm to design an enhanced digital switching control for fast synchronization using an FPGA. The control algorithm was developed based on zero-crossing detection (ZCD) and digital phase-locked loop (PLL) modeling techniques using the hardware description language (HDL) and a combination of digital logic blocks in Quartus II software, where the proposed switching was applied using the square-wave switching technique through a 300-watt full-bridge experimental prototype. The performance of the proposed technique was studied, where the total harmonic distortion (THD) for voltage and current resulted in a percentage reduction of 89.29% and 78.05% for voltage and current, respectively, after filter implementation. Also, the resulting signal synchronized in every half cycle and matched the voltage amplitude, frequency, and phase angle of the grid signal in 10 ms.
Digitally fast synchronization of single-phase grid-tied inverter using FPGA Bakar, Afarulrazi Abu; Sannasy, Balarajan; Poad, Hazwaj Mhd; Sithananthan, Tharnisha; Utomo, Wahyu Mulyo; Rosli, Nor Farisha Diana
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 15, No 4: December 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijpeds.v15.i4.pp2452-2461

Abstract

As interest in alternative energy sources grows, grid-connected inverters are getting more advanced. Thus, to synchronize the output waveform of an inverter with the grid supply system, the frequency and phase angle ought to be consistent. This paper presents an enhanced digital implementation controller for a grid-connected inverter using the sinusoidal pulse-width modulation (SPWM) switching technique via an appropriately designed low-pass filter. The main contribution of the proposed digital controller algorithm is to synchronize with the grid for the next half-cycle. The proposed control technique used the integrated response from the zero-crossing detector (ZCD) circuit for every half-cycle to trigger the digital phase-locked loop (PLL) implemented using field-programmable gate array (FPGA). An experimental 100 W single-phase full-bridge inverter prototype tested and validated the proposed control algorithm to prove the switching approach works. From the experimental results, the proposed control algorithm demonstrates synchronization with the grid voltage within 8 ms during startup. Furthermore, it exhibits the ability to adapt to phase changes when subjected to a distorted grid, achieving synchronization within 42 ms. This research also emphasizes synchronization between the grid waveform and the inverter output via the phase angle difference.
Co-Authors Bakar, Afarulrazi Abu Poad, Hazwaj Mhd Rosli, Nor Farisha Diana Sithananthan, Tharnisha Taufik Taufik Wahyu Mulyo Utomo