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All Journal International Journal of Power Electronics and Drive Systems (IJPEDS)
Manivannan, Kalpanadevi
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Control & Systems Engineering Electrical & Electronics Engineering

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Performance analysis for induction motor fed by reduced switch symmetrical multilevel inverter topology Gajula, Ujwala; Manivannan, Kalpanadevi; Reddy, N. Malla
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 15, No 2: June 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijpeds.v15.i2.pp925-934

Abstract

Due to its capacity to supply more voltage levels than conventional 2-level inverters, multilevel inverters have attracted a lot of attention in recent years. Multilevel inverters may produce output waveforms that nearly approximate sinusoidal waveforms because to this characteristic, which also significantly lowers harmonic distortion. In many different power conversion systems, the introduction of reduced switch symmetrical multilevel inverter topologies has drawn significant interest. Numerous benefits, such as higher output voltage quality, reduced harmonic distortions, and increased power conversion efficiency, are provided by these novel topologies. The inclusion of these inverters in the feeding of induction motors is one of their many prominent uses. In this paper, a generalized topology is presented that generates nine levels using nine switching devices. To reduce complexity, switching pulses are generated using a low frequency pulse width modulation technique. MATLAB/Simulink is used to analyze the performance assessment of a unique three-phase symmetric cascaded multilevel inverter-based reduced switch symmetrical inverter fed induction motor drive, brushless DC (BLDC) motor and grid has been verified. According to the findings the total harmonic distortion (THD) is found to be 15% for a three-phase system and as the number of levels increases to 17 level the THD is 7.10%.
Solar PV based seventeen level reduced switch symmetrical multilevel inverter topology fed induction motor Gajula, Ujwala; Manivannan, Kalpanadevi; Reddy, Nomula Malla
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 15, No 2: June 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijpeds.v15.i2.pp1009-1016

Abstract

Multilevel inverters have received a lot of interest in recent years due to their ability to deliver more voltage levels than typical two-level inverters. Because of this property, multilevel inverters can produce output waveforms that closely resemble sinusoidal waveforms, lowering harmonic distortion dramatically. The emergence of reduced switch symmetrical multilevel inverter topologies has developed the curiosity of many different power conversion systems. These new topologies offer numerous advantages, including greater output voltage quality, fewer harmonic distortions, and increased power conversion efficiency. The inclusion of these inverters in the feeding of induction motors is one of their many prominent uses. A 17 levels of multi-level inverter (MLI) topology is presented with reduced switch count and harmonic reduction for power quality improvement. The inverter is fed by isolated equal photovoltaic panels which act as direct current or DC source. To reduce complexity, switching pulses are generated using hybrid pulse width modulation technique which is designed as controller. Through the use of MATLAB/Simulink, the performance assessment of a unique cascaded multilevel inverter-based reduced switch symmetrical inverter feeding an induction motor drive has been verified. The harmonic distortion with reduced switches obtained is 7.47% which is comparatively less than when compared with conventional cascaded H-bridge topology.
Co-Authors Gajula, Ujwala Reddy, N. Malla Reddy, Nomula Malla